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authorStefan Roese <sr@denx.de>2014-03-04 15:34:35 +0100
committerTom Rini <trini@ti.com>2014-03-07 10:59:06 -0500
commit345b77bacabb84a00c7508471ab560b452910240 (patch)
treeebfd90c103d0129cf16b07912d2a86d2b75bae5d /board/esd
parentdc116bd6c4b5cb1caf6621f282ac5156d1509bef (diff)
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ppc4xx: Remove 4xx NAND booting support
As ppc4xx currently only supports the deprecated nand_spl infrastructure and nobody seems to have time / resources to port this over to the newer SPL infrastructure, lets remove NAND booting completely. This should not affect the "normal", non NAND-booting ppc4xx platforms that are currently supported. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Wolfgang Denk <wd@denx.de> Cc: Tirumala Marri <tmarri@apm.com> Cc: Matthias Fuchs <matthias.fuchs@esd.eu> Cc: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Tom Rini <trini@ti.com> Tested-by: Matthias Fuchs <matthias.fuchs@esd.eu>
Diffstat (limited to 'board/esd')
-rw-r--r--board/esd/pmc440/init.S32
-rw-r--r--board/esd/pmc440/pmc440.c8
2 files changed, 0 insertions, 40 deletions
diff --git a/board/esd/pmc440/init.S b/board/esd/pmc440/init.S
index cc8030b..1f26fad 100644
--- a/board/esd/pmc440/init.S
+++ b/board/esd/pmc440/init.S
@@ -27,11 +27,7 @@ tlbtab:
* BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the
* speed up boot process. It is patched after relocation to enable SA_I
*/
-#ifndef CONFIG_NAND_SPL
tlbentry( CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M, CONFIG_SYS_BOOT_BASE_ADDR, 1, AC_RWX | SA_G )
-#else
- tlbentry( CONFIG_SYS_NAND_BOOT_SPL_SRC, SZ_4K, CONFIG_SYS_NAND_BOOT_SPL_SRC, 1, AC_RWX | SA_G )
-#endif
/* TLB entries for DDR2 SDRAM are generated dynamically */
@@ -71,31 +67,3 @@ tlbtab:
/* TODO: what about high IO space */
tlbtab_end
-
-#if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
- /*
- * For NAND booting the first TLB has to be reconfigured to full size
- * and with caching disabled after running from RAM!
- */
-#define TLB00 TLB0(CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M)
-#define TLB01 TLB1(CONFIG_SYS_BOOT_BASE_ADDR, 1)
-#define TLB02 TLB2(AC_RWX | SA_IG)
-
- .globl reconfig_tlb0
-reconfig_tlb0:
- sync
- isync
- addi r4,r0,0x0000 /* TLB entry #0 */
- lis r5,TLB00@h
- ori r5,r5,TLB00@l
- tlbwe r5,r4,0x0000 /* Save it out */
- lis r5,TLB01@h
- ori r5,r5,TLB01@l
- tlbwe r5,r4,0x0001 /* Save it out */
- lis r5,TLB02@h
- ori r5,r5,TLB02@l
- tlbwe r5,r4,0x0002 /* Save it out */
- sync
- isync
- blr
-#endif
diff --git a/board/esd/pmc440/pmc440.c b/board/esd/pmc440/pmc440.c
index 88fc5f7..e86996c 100644
--- a/board/esd/pmc440/pmc440.c
+++ b/board/esd/pmc440/pmc440.c
@@ -229,19 +229,11 @@ int misc_init_r(void)
gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
gd->bd->bi_flashoffset = 0;
-#if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
- mtdcr(EBC0_CFGADDR, PB2CR);
-#else
mtdcr(EBC0_CFGADDR, PB0CR);
-#endif
pbcr = mfdcr(EBC0_CFGDATA);
size_val = ffs(gd->bd->bi_flashsize) - 21;
pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17);
-#if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
- mtdcr(EBC0_CFGADDR, PB2CR);
-#else
mtdcr(EBC0_CFGADDR, PB0CR);
-#endif
mtdcr(EBC0_CFGDATA, pbcr);
/*