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authorJagan Teki <jagan@amarulasolutions.com>2016-12-06 00:00:53 +0100
committerStefano Babic <sbabic@denx.de>2016-12-16 17:15:27 +0100
commite920f607793a0846b3837924e8ea5e95f2adc29b (patch)
tree7b3b568202e85e38003707d8f22382e3d7c7d130 /board/engicam/icorem6
parent65613cada2be42392ec7b0d9be94d38b9a17ba9f (diff)
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icorem6: Use CONFIG_DM_ETH support
Use CONFIG_DM_ETH and remove board_eth_init code from board files. Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Michael Trimarchi <michael@amarulasolutions.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Diffstat (limited to 'board/engicam/icorem6')
-rw-r--r--board/engicam/icorem6/icorem6.c71
1 files changed, 0 insertions, 71 deletions
diff --git a/board/engicam/icorem6/icorem6.c b/board/engicam/icorem6/icorem6.c
index c152007..587775e 100644
--- a/board/engicam/icorem6/icorem6.c
+++ b/board/engicam/icorem6/icorem6.c
@@ -7,8 +7,6 @@
*/
#include <common.h>
-#include <miiphy.h>
-#include <netdev.h>
#include <asm/io.h>
#include <asm/gpio.h>
@@ -27,80 +25,11 @@ DECLARE_GLOBAL_DATA_PTR;
PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
-#define ENET_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
- PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
- PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
-
static iomux_v3_cfg_t const uart4_pads[] = {
IOMUX_PADS(PAD_KEY_COL0__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
IOMUX_PADS(PAD_KEY_ROW0__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
};
-static iomux_v3_cfg_t const enet_pads[] = {
- IOMUX_PADS(PAD_ENET_CRS_DV__ENET_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL)),
- IOMUX_PADS(PAD_GPIO_16__ENET_REF_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL | PAD_CTL_SRE_FAST)),
- IOMUX_PADS(PAD_ENET_TX_EN__ENET_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL)),
- IOMUX_PADS(PAD_ENET_RXD1__ENET_RX_DATA1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
- IOMUX_PADS(PAD_ENET_RXD0__ENET_RX_DATA0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
- IOMUX_PADS(PAD_ENET_TXD1__ENET_TX_DATA1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
- IOMUX_PADS(PAD_ENET_TXD0__ENET_TX_DATA0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
- IOMUX_PADS(PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
- IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL)),
- IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | MUX_PAD_CTRL(NO_PAD_CTRL)),
-};
-
-#ifdef CONFIG_FEC_MXC
-#define ENET_PHY_RST IMX_GPIO_NR(7, 12)
-static int setup_fec(void)
-{
- struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
- struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
- s32 timeout = 100000;
- u32 reg = 0;
- int ret;
-
- /* Enable fec clock */
- setbits_le32(&ccm->CCGR1, MXC_CCM_CCGR1_ENET_MASK);
-
- /* use 50MHz */
- ret = enable_fec_anatop_clock(0, ENET_50MHZ);
- if (ret)
- return ret;
-
- /* Enable PLLs */
- reg = readl(&anatop->pll_enet);
- reg &= ~BM_ANADIG_PLL_SYS_POWERDOWN;
- writel(reg, &anatop->pll_enet);
- reg = readl(&anatop->pll_enet);
- reg |= BM_ANADIG_PLL_SYS_ENABLE;
- while (timeout--) {
- if (readl(&anatop->pll_enet) & BM_ANADIG_PLL_SYS_LOCK)
- break;
- }
- if (timeout <= 0)
- return -EIO;
- reg &= ~BM_ANADIG_PLL_SYS_BYPASS;
- writel(reg, &anatop->pll_enet);
-
- /* reset the phy */
- gpio_direction_output(ENET_PHY_RST, 0);
- udelay(10000);
- gpio_set_value(ENET_PHY_RST, 1);
-
- return 0;
-}
-
-int board_eth_init(bd_t *bis)
-{
- int ret;
-
- SETUP_IOMUX_PADS(enet_pads);
- setup_fec();
-
- return ret = cpu_eth_init(bis);
-}
-#endif
-
#ifdef CONFIG_NAND_MXS
#define GPMI_PAD_CTRL0 (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP)