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authorHeiko Schocher <hs@denx.de>2011-01-13 08:25:00 +0100
committerWolfgang Denk <wd@denx.de>2011-01-18 23:34:26 +0100
commit466f0137e8661fb62cbece1ce764f8369080c6e8 (patch)
tree4662e64737dbf3baa19f0f6f87831393607cffa8 /board/digsy_mtc
parent1514579fbfb4237e5ac6dfc5c67742765ea7c95c (diff)
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mpc5200, digsy_mtc: add support for rev5 board version
difference to previous board version: - M29W128GH flash from Numonyx - SDRAM ISSI IS45S16800 (Option A2 105°C) - rev5 uses RTC RV-3029-C2 - update cs0 and cs1 baseaddr and length depending on the detected flash size. - added Werner Pfister <Pfister_Werner@intercontrol.de> as maintainer for the digsy board variants - As the M29W128GH needs a special flash_cmd_reset() document that in the new file doc/README.cfi. - move "#endif /* CONFIG_CMD_IDE */" to the right place - remove LOWBOOT config option for digsy_mtc and digsy_mtc_rev5 boards - change doc/README.cfi as Stefan Roese suggested Signed-off-by: Heiko Schocher <hs@denx.de> Signed-off-by: Stefan Roese <sr@denx.de> Acked-by: Detlev Zundel <dzu@denx.de> cc: Wolfgang Denk <hs@denx.de> cc: Stefan Roese <sr@denx.de> cc: Werner Pfister <Pfister_Werner@intercontrol.de> cc: Detlev Zundel <dzu@denx.de>
Diffstat (limited to 'board/digsy_mtc')
-rw-r--r--board/digsy_mtc/digsy_mtc.c109
-rw-r--r--board/digsy_mtc/is45s16800a2.h31
2 files changed, 138 insertions, 2 deletions
diff --git a/board/digsy_mtc/digsy_mtc.c b/board/digsy_mtc/digsy_mtc.c
index cc6087b..afb0948 100644
--- a/board/digsy_mtc/digsy_mtc.c
+++ b/board/digsy_mtc/digsy_mtc.c
@@ -39,12 +39,29 @@
#include <asm/processor.h>
#include <asm/io.h>
#include "eeprom.h"
+#if defined(CONFIG_DIGSY_REV5)
+#include "is45s16800a2.h"
+#include <mtd/cfi_flash.h>
+#else
#include "is42s16800a-7t.h"
+#endif
+#include <libfdt.h>
DECLARE_GLOBAL_DATA_PTR;
extern int usb_cpu_init(void);
+#if defined(CONFIG_DIGSY_REV5)
+/*
+ * The M29W128GH needs a specail reset command function,
+ * details see the doc/README.cfi file
+ */
+void flash_cmd_reset(flash_info_t *info)
+{
+ flash_write_cmd(info, 0, 0, AMD_CMD_RESET);
+}
+#endif
+
#ifndef CONFIG_SYS_RAMBOOT
static void sdram_start(int hi_addr)
{
@@ -175,6 +192,9 @@ int checkboard(void)
char *s = getenv("serial#");
puts ("Board: InterControl digsyMTC");
+#if defined(CONFIG_DIGSY_REV5)
+ puts (" rev5");
+#endif
if (s != NULL) {
puts(", ");
puts(s);
@@ -305,12 +325,97 @@ void ide_set_reset(int idereset)
setbits_be32((void *)MPC5XXX_WU_GPIO_ENABLE, (1 << 25));
}
#endif /* CONFIG_IDE_RESET */
+#endif /* CONFIG_CMD_IDE */
#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
+static void ft_delete_node(void *fdt, const char *compat)
+{
+ int off = -1;
+ int ret;
+
+ off = fdt_node_offset_by_compatible(fdt, -1, compat);
+ if (off < 0) {
+ printf("Could not find %s node.\n", compat);
+ return;
+ }
+
+ ret = fdt_del_node(fdt, off);
+ if (ret < 0)
+ printf("Could not delete %s node.\n", compat);
+}
+#if defined(CONFIG_SYS_UPDATE_FLASH_SIZE)
+static void ft_adapt_flash_base(void *blob)
+{
+ flash_info_t *dev = &flash_info[0];
+ int off;
+ struct fdt_property *prop;
+ int len;
+ u32 *reg, *reg2;
+
+ off = fdt_node_offset_by_compatible(blob, -1, "fsl,mpc5200b-lpb");
+ if (off < 0) {
+ printf("Could not find fsl,mpc5200b-lpb node.\n");
+ return;
+ }
+
+ /* found compatible property */
+ prop = fdt_get_property_w(blob, off, "ranges", &len);
+ if (prop) {
+ reg = reg2 = (u32 *)&prop->data[0];
+
+ reg[2] = dev->start[0];
+ reg[3] = dev->size;
+ fdt_setprop(blob, off, "ranges", reg2, len);
+ } else
+ printf("Could not find ranges\n");
+}
+
+extern ulong flash_get_size (phys_addr_t base, int banknum);
+
+/* Update the Flash Baseaddr settings */
+int update_flash_size (int flash_size)
+{
+ volatile struct mpc5xxx_mmap_ctl *mm =
+ (struct mpc5xxx_mmap_ctl *) CONFIG_SYS_MBAR;
+ flash_info_t *dev;
+ int i;
+ int size = 0;
+ unsigned long base = 0x0;
+ u32 *cs_reg = (u32 *)&mm->cs0_start;
+
+ for (i = 0; i < 2; i++) {
+ dev = &flash_info[i];
+
+ if (dev->size) {
+ /* calculate new base addr for this chipselect */
+ base -= dev->size;
+ out_be32(cs_reg, START_REG(base));
+ cs_reg++;
+ out_be32(cs_reg, STOP_REG(base, dev->size));
+ cs_reg++;
+ /* recalculate the sectoraddr in the cfi driver */
+ size += flash_get_size(base, i);
+ }
+ }
+ gd->bd->bi_flashstart = base;
+ return 0;
+}
+#endif /* defined(CONFIG_SYS_UPDATE_FLASH_SIZE) */
+
void ft_board_setup(void *blob, bd_t *bd)
{
ft_cpu_setup(blob, bd);
+ /*
+ * There are 2 RTC nodes in the DTS, so remove
+ * the unneeded node here.
+ */
+#if defined(CONFIG_DIGSY_REV5)
+ ft_delete_node(blob, "dallas,ds1339");
+#else
+ ft_delete_node(blob, "mc,rv3029c2");
+#endif
+#if defined(CONFIG_SYS_UPDATE_FLASH_SIZE)
+ ft_adapt_flash_base(blob);
+#endif
}
#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
-
-#endif /* CONFIG_CMD_IDE */
diff --git a/board/digsy_mtc/is45s16800a2.h b/board/digsy_mtc/is45s16800a2.h
new file mode 100644
index 0000000..6ab5c12
--- /dev/null
+++ b/board/digsy_mtc/is45s16800a2.h
@@ -0,0 +1,31 @@
+/*
+ * (C) Copyright 2010
+ * Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ *
+ * based on:
+ * (C) Copyright 2004-2009
+ * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#define SDRAM_MODE 0x00CD0000
+#define SDRAM_CONTROL 0x50470000
+#define SDRAM_CONFIG1 0xD2322900
+#define SDRAM_CONFIG2 0x8AD70000