summaryrefslogtreecommitdiff
path: root/board/denx/mcvevk/qts
diff options
context:
space:
mode:
authorChin Liang See <clsee@altera.com>2016-09-21 10:25:58 +0800
committerMarek Vasut <marex@denx.de>2016-10-27 08:03:09 +0200
commitb38c1d2f6b11fbfb8eab50522dfc154dbf097956 (patch)
tree29cf68be60e7b9ccfce1e5059f8345314927988c /board/denx/mcvevk/qts
parent0db1ac47ee1e88e3d3784bcdb3a0e1ea277419cc (diff)
downloadu-boot-imx-b38c1d2f6b11fbfb8eab50522dfc154dbf097956.zip
u-boot-imx-b38c1d2f6b11fbfb8eab50522dfc154dbf097956.tar.gz
u-boot-imx-b38c1d2f6b11fbfb8eab50522dfc154dbf097956.tar.bz2
arm: socfpga: mcvevk: Adding handoff for SDRAM ctrlcfg.extratime1
Adding new handoff for SDRAM ctrcfg.extratime1 which is required for stable LPDDR2 operation. Since the board is using DDR3, the handoff is set to default value 0. Signed-off-by: Chin Liang See <clsee@altera.com> Cc: Marek Vasut <marex@denx.de> Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Diffstat (limited to 'board/denx/mcvevk/qts')
-rw-r--r--board/denx/mcvevk/qts/sdram_config.h3
1 files changed, 3 insertions, 0 deletions
diff --git a/board/denx/mcvevk/qts/sdram_config.h b/board/denx/mcvevk/qts/sdram_config.h
index 30c4d7d..ff64f55 100644
--- a/board/denx/mcvevk/qts/sdram_config.h
+++ b/board/denx/mcvevk/qts/sdram_config.h
@@ -49,6 +49,9 @@
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP 5
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT 3
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT 512
+#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR 0
+#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC 0
+#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 0
#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC 0
#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE 0
#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST 0x0