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| author | Stefan Roese <sr@denx.de> | 2016-08-25 16:22:10 +0200 |
|---|---|---|
| committer | Stefan Roese <sr@denx.de> | 2016-09-24 10:00:41 +0200 |
| commit | 9ed00b072be8fe346604eaec805359fa762fcb59 (patch) | |
| tree | 10108077efd7f646af40f62ccfdbe9e3450c794b /board/cadence/xtfpga/README | |
| parent | 8824cfc19a6e4ae23ca8006bb22b7b6f839b09a8 (diff) | |
| download | u-boot-imx-9ed00b072be8fe346604eaec805359fa762fcb59.zip u-boot-imx-9ed00b072be8fe346604eaec805359fa762fcb59.tar.gz u-boot-imx-9ed00b072be8fe346604eaec805359fa762fcb59.tar.bz2 | |
arm: mvebu: theadorable: Configure board for PCIe 2.0 capability
Use a board-specific board_sat_r_get() function to configure the board
for PCIe 2.0 capability (e.g. 5GB/s link speed). Otherwise the default
of 2.5GB/s will be established.
Signed-off-by: Stefan Roese <sr@denx.de>
Diffstat (limited to 'board/cadence/xtfpga/README')
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