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authorJean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>2008-10-16 15:01:15 +0200
committerWolfgang Denk <wd@denx.de>2008-10-18 21:54:03 +0200
commit6d0f6bcf337c5261c08fabe12982178c2c489d76 (patch)
treeae13958ffa9c6b58c2ea97aac07a4ad2f04a350f /board/bf533-stamp
parent71edc271816ec82cf0550dd6980be2da3cc2ad9e (diff)
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rename CFG_ macros to CONFIG_SYS
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Diffstat (limited to 'board/bf533-stamp')
-rw-r--r--board/bf533-stamp/bf533-stamp.c6
-rw-r--r--board/bf533-stamp/u-boot.lds.S4
2 files changed, 5 insertions, 5 deletions
diff --git a/board/bf533-stamp/bf533-stamp.c b/board/bf533-stamp/bf533-stamp.c
index 7a17dfa..a113c40 100644
--- a/board/bf533-stamp/bf533-stamp.c
+++ b/board/bf533-stamp/bf533-stamp.c
@@ -56,11 +56,11 @@ phys_size_t initdram(int board_type)
(" tRCD:%d Cycles; tRP:%d Cycles; tRAS:%d Cycles; tWR:%d Cycles; "
"CAS Latency:%d cycles\n", (SDRAM_tRCD >> 15), (SDRAM_tRP >> 11),
(SDRAM_tRAS >> 6), (SDRAM_tWR >> 19), (SDRAM_CL >> 2));
- printf("SDRAM Begin: 0x%x\n", CFG_SDRAM_BASE);
+ printf("SDRAM Begin: 0x%x\n", CONFIG_SYS_SDRAM_BASE);
printf("Bank size = %d MB\n", 128);
#endif
- gd->bd->bi_memstart = CFG_SDRAM_BASE;
- gd->bd->bi_memsize = CFG_MAX_RAM_SIZE;
+ gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;
+ gd->bd->bi_memsize = CONFIG_SYS_MAX_RAM_SIZE;
return (gd->bd->bi_memsize);
}
diff --git a/board/bf533-stamp/u-boot.lds.S b/board/bf533-stamp/u-boot.lds.S
index 4e7fd7c..97ebd79 100644
--- a/board/bf533-stamp/u-boot.lds.S
+++ b/board/bf533-stamp/u-boot.lds.S
@@ -36,7 +36,7 @@
* for different CPU's which may lack non-cache L1 data.
*/
#ifndef L1_DATA_B_SRAM
-# define L1_DATA_B_SRAM CFG_MONITOR_BASE
+# define L1_DATA_B_SRAM CONFIG_SYS_MONITOR_BASE
# define L1_DATA_B_SRAM_SIZE 0
#endif
@@ -45,7 +45,7 @@ OUTPUT_ARCH(bfin)
/* The 0xC offset is so we don't clobber the tiny LDR jump block. */
MEMORY
{
- ram : ORIGIN = CFG_MONITOR_BASE, LENGTH = CFG_MONITOR_LEN
+ ram : ORIGIN = CONFIG_SYS_MONITOR_BASE, LENGTH = CONFIG_SYS_MONITOR_LEN
l1_code : ORIGIN = L1_INST_SRAM+0xC, LENGTH = L1_INST_SRAM_SIZE
l1_data : ORIGIN = L1_DATA_B_SRAM, LENGTH = L1_DATA_B_SRAM_SIZE
}