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| author | Anatolij Gustschin <agust@denx.de> | 2013-02-08 00:03:49 +0000 |
|---|---|---|
| committer | Wolfgang Denk <wd@denx.de> | 2013-03-09 08:23:02 +0100 |
| commit | a615dfda8c2041dd98ecd238d45f3bc35e495b44 (patch) | |
| tree | b177e8e05649ba7da7f8f7dcfe309fb29b7aef68 /board/bc3450/mt48lc16m16a2-75.h | |
| parent | fcc7fe425183f9ec95fba33d041eb359d0a3a598 (diff) | |
| download | u-boot-imx-a615dfda8c2041dd98ecd238d45f3bc35e495b44.zip u-boot-imx-a615dfda8c2041dd98ecd238d45f3bc35e495b44.tar.gz u-boot-imx-a615dfda8c2041dd98ecd238d45f3bc35e495b44.tar.bz2 | |
mpc512x: Adjust the DRAM init sequence to the datasheet spec
Do maintain a 200 usecs period of stable power and clock before
asserting the CKE signal and sending commands, have at least 200
DRAM clock cycles pass after initialization before data access.
Signed-off-by: Anatolij Gustschin <agust@denx.de>
Diffstat (limited to 'board/bc3450/mt48lc16m16a2-75.h')
0 files changed, 0 insertions, 0 deletions