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| author | Andreas Bießmann <andreas.devel@googlemail.com> | 2015-02-06 23:06:42 +0100 |
|---|---|---|
| committer | Andreas Bießmann <andreas.devel@googlemail.com> | 2015-02-17 22:52:40 +0100 |
| commit | e9ed41cc5c684b4b08988934544449eb782c14db (patch) | |
| tree | 3739cdbd76c4bdd276f08166f63179e54085c03b /board/atmel/atngw100mkii/atngw100mkii.c | |
| parent | 26db7903f5102b8cf5570237ccbfc7f2c0dfd7aa (diff) | |
| download | u-boot-imx-e9ed41cc5c684b4b08988934544449eb782c14db.zip u-boot-imx-e9ed41cc5c684b4b08988934544449eb782c14db.tar.gz u-boot-imx-e9ed41cc5c684b4b08988934544449eb782c14db.tar.bz2 | |
avr32: rename mmu.h definitions
Prefix mmu.h PAGE_xxx definitions with MMU_ in order to prevent a naming
conflict with other definitions.
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
Diffstat (limited to 'board/atmel/atngw100mkii/atngw100mkii.c')
| -rw-r--r-- | board/atmel/atngw100mkii/atngw100mkii.c | 18 |
1 files changed, 9 insertions, 9 deletions
diff --git a/board/atmel/atngw100mkii/atngw100mkii.c b/board/atmel/atngw100mkii/atngw100mkii.c index 72d19e4..912ea10 100644 --- a/board/atmel/atngw100mkii/atngw100mkii.c +++ b/board/atmel/atngw100mkii/atngw100mkii.c @@ -23,21 +23,21 @@ DECLARE_GLOBAL_DATA_PTR; struct mmu_vm_range mmu_vmr_table[CONFIG_SYS_NR_VM_REGIONS] = { { /* Atmel AT49BV640D 8 MiB x16 NOR flash on NCS0 */ - .virt_pgno = CONFIG_SYS_FLASH_BASE >> PAGE_SHIFT, - .nr_pages = CONFIG_SYS_FLASH_SIZE >> PAGE_SHIFT, - .phys = (CONFIG_SYS_FLASH_BASE >> PAGE_SHIFT) + .virt_pgno = CONFIG_SYS_FLASH_BASE >> MMU_PAGE_SHIFT, + .nr_pages = CONFIG_SYS_FLASH_SIZE >> MMU_PAGE_SHIFT, + .phys = (CONFIG_SYS_FLASH_BASE >> MMU_PAGE_SHIFT) | MMU_VMR_CACHE_NONE, }, { /* Micron MT29F2G16AAD 256 MiB x16 NAND flash on NCS3 */ - .virt_pgno = EBI_SRAM_CS3_BASE >> PAGE_SHIFT, - .nr_pages = EBI_SRAM_CS3_SIZE >> PAGE_SHIFT, - .phys = (EBI_SRAM_CS3_BASE >> PAGE_SHIFT) + .virt_pgno = EBI_SRAM_CS3_BASE >> MMU_PAGE_SHIFT, + .nr_pages = EBI_SRAM_CS3_SIZE >> MMU_PAGE_SHIFT, + .phys = (EBI_SRAM_CS3_BASE >> MMU_PAGE_SHIFT) | MMU_VMR_CACHE_NONE, }, { /* 2x16-bit ISSI IS42S16320B 64 MiB SDRAM (128 MiB total) */ - .virt_pgno = CONFIG_SYS_SDRAM_BASE >> PAGE_SHIFT, - .nr_pages = EBI_SDRAM_SIZE >> PAGE_SHIFT, - .phys = (CONFIG_SYS_SDRAM_BASE >> PAGE_SHIFT) + .virt_pgno = CONFIG_SYS_SDRAM_BASE >> MMU_PAGE_SHIFT, + .nr_pages = EBI_SDRAM_SIZE >> MMU_PAGE_SHIFT, + .phys = (CONFIG_SYS_SDRAM_BASE >> MMU_PAGE_SHIFT) | MMU_VMR_CACHE_WRBACK, }, }; |