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| author | Sandor Yu <R01008@freescale.com> | 2014-07-04 17:13:58 +0800 |
|---|---|---|
| committer | Ye Li <ye.li@nxp.com> | 2017-04-05 14:04:31 +0800 |
| commit | db38481f18659a37ea81a4149566f1ff9e46b304 (patch) | |
| tree | b586e84bf256764a3b4b0dbbe3e1c8853535eca1 /board/aristainetos/ddr-setup2.cfg | |
| parent | 50b358a7eb30f6299923e8f35d10b77485c87472 (diff) | |
| download | u-boot-imx-db38481f18659a37ea81a4149566f1ff9e46b304.zip u-boot-imx-db38481f18659a37ea81a4149566f1ff9e46b304.tar.gz u-boot-imx-db38481f18659a37ea81a4149566f1ff9e46b304.tar.bz2 | |
ENGR00321299 gis: clean csi0 input mux set bit in GPR
When gis enable in uboot, the CSI0 input mux select setting
to vadc module, clean the bit when gis disabled.
Signed-off-by: Sandor Yu <R01008@freescale.com>
(cherry picked from commit ae66b17b7da3be50dc81ca636b67e8e879f52e26)
(cherry picked from commit c83fd326e810c2fff44b8b02e78406d5d04c977c)
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
(cherry picked from commit d6e803ed5f51d31ebe7e9d178aa11f16401b7fc8)
(cherry picked from commit 2065b417ae93436736e49ca66b66aa0791d003fe)
Diffstat (limited to 'board/aristainetos/ddr-setup2.cfg')
0 files changed, 0 insertions, 0 deletions