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| author | Stefan Agner <stefan@agner.ch> | 2014-08-19 17:54:27 +0200 |
|---|---|---|
| committer | Stefano Babic <sbabic@denx.de> | 2014-09-09 16:52:44 +0200 |
| commit | a3db78d8870c8fb5bc0b1acd73bdc998d0d34200 (patch) | |
| tree | ae8bb037cb325b841b003320dda5b7d327fa5b26 /board/aristainetos/ddr-setup.cfg | |
| parent | 2d59e3ecd202e64a164b813a9ce9da2fd74f3e6a (diff) | |
| download | u-boot-imx-a3db78d8870c8fb5bc0b1acd73bdc998d0d34200.zip u-boot-imx-a3db78d8870c8fb5bc0b1acd73bdc998d0d34200.tar.gz u-boot-imx-a3db78d8870c8fb5bc0b1acd73bdc998d0d34200.tar.bz2 | |
arm: vf610: lpuart: fix status register handling
The status register 1 (S1) is not writeable, hence we should not
write it. In order to clear the RDRF flag we only need to read
the data register.
Also, when stressing U-Boot a lot with serial input, an overflow can
occur which asserts the S1_OR flag (while not asserting the S1_RDRF
flag). To clear this flag we again just need to read the data
register, hence add this flag to the abort conditions for the while
loop.
Insert a compiler barrier to make sure reading the data register
gets executed after reading the status register.
Signed-off-by: Stefan Agner <stefan@agner.ch>
Diffstat (limited to 'board/aristainetos/ddr-setup.cfg')
0 files changed, 0 insertions, 0 deletions