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authorStefan Roese <sr@denx.de>2014-03-04 15:34:35 +0100
committerTom Rini <trini@ti.com>2014-03-07 10:59:06 -0500
commit345b77bacabb84a00c7508471ab560b452910240 (patch)
treeebfd90c103d0129cf16b07912d2a86d2b75bae5d /board/amcc/bamboo/bamboo.c
parentdc116bd6c4b5cb1caf6621f282ac5156d1509bef (diff)
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ppc4xx: Remove 4xx NAND booting support
As ppc4xx currently only supports the deprecated nand_spl infrastructure and nobody seems to have time / resources to port this over to the newer SPL infrastructure, lets remove NAND booting completely. This should not affect the "normal", non NAND-booting ppc4xx platforms that are currently supported. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Wolfgang Denk <wd@denx.de> Cc: Tirumala Marri <tmarri@apm.com> Cc: Matthias Fuchs <matthias.fuchs@esd.eu> Cc: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Tom Rini <trini@ti.com> Tested-by: Matthias Fuchs <matthias.fuchs@esd.eu>
Diffstat (limited to 'board/amcc/bamboo/bamboo.c')
-rw-r--r--board/amcc/bamboo/bamboo.c17
1 files changed, 0 insertions, 17 deletions
diff --git a/board/amcc/bamboo/bamboo.c b/board/amcc/bamboo/bamboo.c
index 84bbacf..c8d0963 100644
--- a/board/amcc/bamboo/bamboo.c
+++ b/board/amcc/bamboo/bamboo.c
@@ -16,7 +16,6 @@ void ext_bus_cntlr_init(void);
void configure_ppc440ep_pins(void);
int is_nand_selected(void);
-#if !(defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL))
/*************************************************************************
*
* Bamboo has one bank onboard sdram (plus DIMM)
@@ -178,7 +177,6 @@ const unsigned char cfg_simulate_spd_eeprom[128] = {
0,
0
};
-#endif
#if 0
{ /* GPIO Alternate1 Alternate2 Alternate3 */
@@ -440,15 +438,11 @@ int checkboard(void)
phys_size_t initdram (int board_type)
{
-#if !(defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL))
long dram_size;
dram_size = spd_sdram();
return dram_size;
-#else
- return CONFIG_SYS_MBYTES_SDRAM << 20;
-#endif
}
/*----------------------------------------------------------------------------+
@@ -1794,23 +1788,12 @@ void configure_ppc440ep_pins(void)
if (ppc440ep_core_selection[NAND_FLASH] == CORE_SELECTED)
{
update_ndfc_ios(gpio_tab);
-
-#if !(defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL))
mtsdr(SDR0_CUST0, SDR0_CUST0_MUX_NDFC_SEL |
SDR0_CUST0_NDFC_ENABLE |
SDR0_CUST0_NDFC_BW_8_BIT |
SDR0_CUST0_NDFC_ARE_MASK |
SDR0_CUST0_CHIPSELGAT_EN1 |
SDR0_CUST0_CHIPSELGAT_EN2);
-#else
- mtsdr(SDR0_CUST0, SDR0_CUST0_MUX_NDFC_SEL |
- SDR0_CUST0_NDFC_ENABLE |
- SDR0_CUST0_NDFC_BW_8_BIT |
- SDR0_CUST0_NDFC_ARE_MASK |
- SDR0_CUST0_CHIPSELGAT_EN0 |
- SDR0_CUST0_CHIPSELGAT_EN2);
-#endif
-
ndfc_selection_in_fpga();
}
else