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authorStefan Roese <sr@denx.de>2009-09-09 16:25:29 +0200
committerStefan Roese <sr@denx.de>2009-09-11 10:35:58 +0200
commitd1c3b27525b664e8c4db6bb173eed51bfc8220de (patch)
treec00f3d0bcfbd5fcc1954cc9cefdbc4c9c41f41ea /board/amcc/acadia/pll.c
parente7963772eb78a6aa1fa65063d64eab3a8626daac (diff)
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ppc4xx: Big cleanup of PPC4xx defines
This patch cleans up multiple issues of the 4xx register (mostly DCR, SDR, CPR, etc) definitions: - Change lower case defines to upper case (plb4_acr -> PLB4_ACR) - Change the defines to better match the names from the user's manuals (e.g. cprpllc -> CPR0_PLLC) - Removal of some unused defines Please test this patch intensive on your PPC4xx platform. Even though I tried not to break anything and tested successfully on multiple 4xx AMCC platforms, testing on custom platforms is recommended. Signed-off-by: Stefan Roese <sr@denx.de>
Diffstat (limited to 'board/amcc/acadia/pll.c')
-rw-r--r--board/amcc/acadia/pll.c52
1 files changed, 26 insertions, 26 deletions
diff --git a/board/amcc/acadia/pll.c b/board/amcc/acadia/pll.c
index 9dcce35..b63813c 100644
--- a/board/amcc/acadia/pll.c
+++ b/board/amcc/acadia/pll.c
@@ -51,11 +51,11 @@ void board_pll_init_f(void)
*/
/* Initialize PLL */
- mtcpr(cprpllc, 0x0000033c);
- mtcpr(cprplld, 0x0c010200);
- mtcpr(cprprimad, 0x04060c0c);
- mtcpr(cprperd0, 0x000c0000); /* SPI clk div. eq. OPB clk div. */
- mtcpr(cprclkupd, 0x40000000);
+ mtcpr(CPR0_PLLC, 0x0000033c);
+ mtcpr(CPR0_PLLD, 0x0c010200);
+ mtcpr(CPC0_PRIMAD, 0x04060c0c);
+ mtcpr(CPC0_PERD0, 0x000c0000); /* SPI clk div. eq. OPB clk div. */
+ mtcpr(CPR0_CLKUP, 0x40000000);
}
#elif defined(PLLMR0_266_160_80)
@@ -83,13 +83,13 @@ void board_pll_init_f(void)
*/
/* Initialize PLL */
- mtcpr(cprpllc, 0x20000238);
- mtcpr(cprplld, 0x03010400);
- mtcpr(cprprimad, 0x03050a0a);
- mtcpr(cprperc0, 0x00000000);
- mtcpr(cprperd0, 0x070a0707); /* SPI clk div. eq. OPB clk div. */
- mtcpr(cprperd1, 0x07323200);
- mtcpr(cprclkupd, 0x40000000);
+ mtcpr(CPR0_PLLC, 0x20000238);
+ mtcpr(CPR0_PLLD, 0x03010400);
+ mtcpr(CPC0_PRIMAD, 0x03050a0a);
+ mtcpr(CPC0_PERC0, 0x00000000);
+ mtcpr(CPC0_PERD0, 0x070a0707); /* SPI clk div. eq. OPB clk div. */
+ mtcpr(CPC0_PERD1, 0x07323200);
+ mtcpr(CPR0_CLKUP, 0x40000000);
}
#elif defined(PLLMR0_333_166_83)
@@ -117,12 +117,12 @@ void board_pll_init_f(void)
*/
/* Initialize PLL */
- mtcpr(cprpllc, 0x0000033C);
- mtcpr(cprplld, 0x0a010000);
- mtcpr(cprprimad, 0x02040808);
- mtcpr(cprperd0, 0x02080505); /* SPI clk div. eq. OPB clk div. */
- mtcpr(cprperd1, 0xA6A60300);
- mtcpr(cprclkupd, 0x40000000);
+ mtcpr(CPR0_PLLC, 0x0000033C);
+ mtcpr(CPR0_PLLD, 0x0a010000);
+ mtcpr(CPC0_PRIMAD, 0x02040808);
+ mtcpr(CPC0_PERD0, 0x02080505); /* SPI clk div. eq. OPB clk div. */
+ mtcpr(CPC0_PERD1, 0xA6A60300);
+ mtcpr(CPR0_CLKUP, 0x40000000);
}
#elif defined(PLLMR0_100_100_12)
@@ -143,12 +143,12 @@ void board_pll_init_f(void)
*/
/* Initialize PLL */
- mtcpr(cprpllc, 0x000003BC);
- mtcpr(cprplld, 0x06060600);
- mtcpr(cprprimad, 0x02020004);
- mtcpr(cprperd0, 0x04002828); /* SPI clk div. eq. OPB clk div. */
- mtcpr(cprperd1, 0xC8C81600);
- mtcpr(cprclkupd, 0x40000000);
+ mtcpr(CPR0_PLLC, 0x000003BC);
+ mtcpr(CPR0_PLLD, 0x06060600);
+ mtcpr(CPC0_PRIMAD, 0x02020004);
+ mtcpr(CPC0_PERD0, 0x04002828); /* SPI clk div. eq. OPB clk div. */
+ mtcpr(CPC0_PERD1, 0xC8C81600);
+ mtcpr(CPR0_CLKUP, 0x40000000);
}
#endif /* CPU_<speed>_405EZ */
@@ -167,12 +167,12 @@ unsigned long get_tbclk(void)
/*
* Read PLL Mode registers
*/
- mfcpr(cprplld, cpr_plld);
+ mfcpr(CPR0_PLLD, cpr_plld);
/*
* Read CPR_PRIMAD register
*/
- mfcpr(cprprimad, cpr_primad);
+ mfcpr(CPC0_PRIMAD, cpr_primad);
/*
* Determine CPU clock frequency