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| author | Stefan Roese <sr@denx.de> | 2014-03-04 15:34:35 +0100 |
|---|---|---|
| committer | Tom Rini <trini@ti.com> | 2014-03-07 10:59:06 -0500 |
| commit | 345b77bacabb84a00c7508471ab560b452910240 (patch) | |
| tree | ebfd90c103d0129cf16b07912d2a86d2b75bae5d /board/amcc/acadia/pll.c | |
| parent | dc116bd6c4b5cb1caf6621f282ac5156d1509bef (diff) | |
| download | u-boot-imx-345b77bacabb84a00c7508471ab560b452910240.zip u-boot-imx-345b77bacabb84a00c7508471ab560b452910240.tar.gz u-boot-imx-345b77bacabb84a00c7508471ab560b452910240.tar.bz2 | |
ppc4xx: Remove 4xx NAND booting support
As ppc4xx currently only supports the deprecated nand_spl infrastructure
and nobody seems to have time / resources to port this over to the newer
SPL infrastructure, lets remove NAND booting completely.
This should not affect the "normal", non NAND-booting ppc4xx platforms
that are currently supported.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Tirumala Marri <tmarri@apm.com>
Cc: Matthias Fuchs <matthias.fuchs@esd.eu>
Cc: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Tom Rini <trini@ti.com>
Tested-by: Matthias Fuchs <matthias.fuchs@esd.eu>
Diffstat (limited to 'board/amcc/acadia/pll.c')
| -rw-r--r-- | board/amcc/acadia/pll.c | 42 |
1 files changed, 0 insertions, 42 deletions
diff --git a/board/amcc/acadia/pll.c b/board/amcc/acadia/pll.c index d74b725..d868582 100644 --- a/board/amcc/acadia/pll.c +++ b/board/amcc/acadia/pll.c @@ -135,45 +135,3 @@ void board_pll_init_f(void) mtcpr(CPR0_CLKUP, 0x40000000); } #endif /* CPU_<speed>_405EZ */ - -#if defined(CONFIG_NAND_SPL) || defined(CONFIG_SPI_SPL) -/* - * Get timebase clock frequency - */ -unsigned long get_tbclk(void) -{ - unsigned long cpr_plld; - unsigned long cpr_primad; - unsigned long primad_cpudv; - unsigned long pllFbkDiv; - unsigned long freqProcessor; - - /* - * Read PLL Mode registers - */ - mfcpr(CPR0_PLLD, cpr_plld); - - /* - * Read CPR_PRIMAD register - */ - mfcpr(CPR0_PRIMAD, cpr_primad); - - /* - * Determine CPU clock frequency - */ - primad_cpudv = ((cpr_primad & PRIMAD_CPUDV_MASK) >> 24); - if (primad_cpudv == 0) - primad_cpudv = 16; - - /* - * Determine FBK_DIV. - */ - pllFbkDiv = ((cpr_plld & PLLD_FBDV_MASK) >> 24); - if (pllFbkDiv == 0) - pllFbkDiv = 256; - - freqProcessor = (CONFIG_SYS_CLK_FREQ * pllFbkDiv) / primad_cpudv; - - return (freqProcessor); -} -#endif /* defined(CONFIG_NAND_SPL) || defined(CONFIG_SPI_SPL) */ |