summaryrefslogtreecommitdiff
path: root/arch
diff options
context:
space:
mode:
authorKim Phillips <kim.phillips@freescale.com>2012-10-29 13:34:38 +0000
committerTom Rini <trini@ti.com>2012-11-04 11:00:36 -0700
commite56143e54f64c849340d448adb0ca5e69a08421b (patch)
tree33367d547ef8fa69bc7aa968801a6b326a81b8f6 /arch
parent2ed2e9121f220673389e2459870a396085287325 (diff)
downloadu-boot-imx-e56143e54f64c849340d448adb0ca5e69a08421b.zip
u-boot-imx-e56143e54f64c849340d448adb0ca5e69a08421b.tar.gz
u-boot-imx-e56143e54f64c849340d448adb0ca5e69a08421b.tar.bz2
powerpc/mpc85xx: sparse fixes
fsl_corenet_serdes.c:485:6: warning: symbol '__soc_serdes_init' was not declared. Should it be static? cpu_init.c:185:6: warning: symbol 'invalidate_cpc' was not declared. Should it be static? bcsr.c:28:27: warning: non-ANSI function declaration of function 'enable_8568mds_duart' bcsr.c:39:33: warning: non-ANSI function declaration of function 'enable_8568mds_flash_write' bcsr.c:46:34: warning: non-ANSI function declaration of function 'disable_8568mds_flash_write' bcsr.c:53:29: warning: non-ANSI function declaration of function 'enable_8568mds_qe_mdio' bcsr.c:28:33: warning: non-ANSI function declaration of function 'enable_8569mds_flash_write' bcsr.c:33:34: warning: non-ANSI function declaration of function 'disable_8569mds_flash_write' bcsr.c:38:28: warning: non-ANSI function declaration of function 'enable_8569mds_qe_uec' bcsr.c:63:47: warning: non-ANSI function declaration of function 'disable_8569mds_brd_eeprom_write_protect' ngpixis.c:245:1: error: directive in argument list ngpixis.c:247:1: error: directive in argument list Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Diffstat (limited to 'arch')
-rw-r--r--arch/powerpc/cpu/mpc85xx/cpu_init.c2
-rw-r--r--arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c2
2 files changed, 2 insertions, 2 deletions
diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c
index 736293c..f01804b 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c
@@ -182,7 +182,7 @@ static void enable_cpc(void)
printf("Corenet Platform Cache: %d KB enabled\n", size);
}
-void invalidate_cpc(void)
+static void invalidate_cpc(void)
{
int i;
cpc_corenet_t *cpc = (cpc_corenet_t *)CONFIG_SYS_FSL_CPC_ADDR;
diff --git a/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c b/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c
index e6b1b1b..7f466ac 100644
--- a/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c
+++ b/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c
@@ -489,7 +489,7 @@ static void wait_for_rstdone(unsigned int bank)
}
-void __soc_serdes_init(void)
+static void __soc_serdes_init(void)
{
/* Allow for SoC-specific initialization in <SOC>_serdes.c */
};