Merge branch 'master' of git://git.denx.de/u-boot-arm

19 files changed, 300 insertions, 12 deletions

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 0d756cb..5ab0254 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -10,6 +10,9 @@ config ARM64
 config HAS_VBAR
         bool
 
+config HAS_THUMB2
+        bool
+
 config CPU_ARM720T
         bool
 
@@ -32,9 +35,11 @@ config CPU_ARM1176
 config CPU_V7
         bool
         select HAS_VBAR
+        select HAS_THUMB2
 
 config CPU_V7M
 	bool
+        select HAS_THUMB2
 
 config CPU_PXA
         bool
diff --git a/arch/arm/cpu/arm926ejs/Makefile b/arch/arm/cpu/arm926ejs/Makefile
index 63fa159..fe78922 100644
--- a/arch/arm/cpu/arm926ejs/Makefile
+++ b/arch/arm/cpu/arm926ejs/Makefile
@@ -20,3 +20,14 @@ obj-$(CONFIG_MX25) += mx25/
 obj-$(CONFIG_MX27) += mx27/
 obj-$(if $(filter mxs,$(SOC)),y) += mxs/
 obj-$(if $(filter spear,$(SOC)),y) += spear/
+
+# some files can only build in ARM or THUMB2, not THUMB1
+
+ifdef CONFIG_SYS_THUMB_BUILD
+ifndef CONFIG_HAS_THUMB2
+
+CFLAGS_cpu.o := -marm
+CFLAGS_cache.o := -marm
+
+endif
+endif
diff --git a/arch/arm/cpu/arm926ejs/cache.c b/arch/arm/cpu/arm926ejs/cache.c
index e5c1a6a..2839c86 100644
--- a/arch/arm/cpu/arm926ejs/cache.c
+++ b/arch/arm/cpu/arm926ejs/cache.c
@@ -82,4 +82,9 @@ void flush_dcache_all(void)
 /*
  * Stub implementations for l2 cache operations
  */
+
 __weak void l2_cache_disable(void) {}
+
+#if defined CONFIG_SYS_THUMB_BUILD
+__weak void invalidate_l2_cache(void) {}
+#endif
diff --git a/arch/arm/cpu/armv7m/stm32f4/flash.c b/arch/arm/cpu/armv7m/stm32f4/flash.c
index e5c6111..dd058bd 100644
--- a/arch/arm/cpu/armv7m/stm32f4/flash.c
+++ b/arch/arm/cpu/armv7m/stm32f4/flash.c
@@ -97,6 +97,9 @@ int flash_erase(flash_info_t *info, int first, int last)
 		while (readl(&STM32_FLASH->sr) & STM32_FLASH_SR_BSY)
 			;
 
+		/* clear old sector number before writing a new one */
+		clrbits_le32(&STM32_FLASH->cr, STM32_FLASH_CR_SNB_MASK);
+
 		if (bank == 0) {
 			setbits_le32(&STM32_FLASH->cr,
 				     (i << STM32_FLASH_CR_SNB_OFFSET));
@@ -114,9 +117,9 @@ int flash_erase(flash_info_t *info, int first, int last)
 			;
 
 		clrbits_le32(&STM32_FLASH->cr, STM32_FLASH_CR_SER);
-		stm32f4_flash_lock(1);
 	}
 
+	stm32f4_flash_lock(1);
 	return 0;
 }
 
diff --git a/arch/arm/cpu/armv8/cache_v8.c b/arch/arm/cpu/armv8/cache_v8.c
index b1ea822..1ece6a2 100644
--- a/arch/arm/cpu/armv8/cache_v8.c
+++ b/arch/arm/cpu/armv8/cache_v8.c
@@ -32,7 +32,7 @@ inline void set_pgtable_table(u64 *page_table, u64 index, u64 *table_addr)
 }
 
 /* to activate the MMU we need to set up virtual memory */
-static void mmu_setup(void)
+__weak void mmu_setup(void)
 {
 	bd_t *bd = gd->bd;
 	u64 *page_table = (u64 *)gd->arch.tlb_addr, i, j;
diff --git a/arch/arm/include/asm/arch-stm32f4/stm32.h b/arch/arm/include/asm/arch-stm32f4/stm32.h
index 3ed3801..7ca6dc3 100644
--- a/arch/arm/include/asm/arch-stm32f4/stm32.h
+++ b/arch/arm/include/asm/arch-stm32f4/stm32.h
@@ -104,6 +104,7 @@ struct stm32_flash_regs {
 #define STM32_FLASH_CR_STRT		(1 << 16)
 #define STM32_FLASH_CR_LOCK		(1 << 31)
 #define STM32_FLASH_CR_SNB_OFFSET	3
+#define STM32_FLASH_CR_SNB_MASK		(15 << STM32_FLASH_CR_SNB_OFFSET)
 
 enum clock {
 	CLOCK_CORE,
diff --git a/arch/arm/include/asm/cache.h b/arch/arm/include/asm/cache.h
index a836e9f..1f63127 100644
--- a/arch/arm/include/asm/cache.h
+++ b/arch/arm/include/asm/cache.h
@@ -16,6 +16,9 @@
 /*
  * Invalidate L2 Cache using co-proc instruction
  */
+#ifdef CONFIG_SYS_THUMB_BUILD
+void invalidate_l2_cache(void);
+#else
 static inline void invalidate_l2_cache(void)
 {
 	unsigned int val=0;
@@ -24,6 +27,7 @@ static inline void invalidate_l2_cache(void)
 		: : "r" (val) : "cc");
 	isb();
 }
+#endif
 
 void l2_cache_enable(void);
 void l2_cache_disable(void);
diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h
index cfc7834..71b3108 100644
--- a/arch/arm/include/asm/system.h
+++ b/arch/arm/include/asm/system.h
@@ -17,6 +17,7 @@
 #define PGTABLE_SIZE	(0x10000)
 /* 2MB granularity */
 #define MMU_SECTION_SHIFT	21
+#define MMU_SECTION_SIZE	(1 << MMU_SECTION_SHIFT)
 
 #ifndef __ASSEMBLY__
 
@@ -278,11 +279,6 @@ enum {
  */
 void mmu_page_table_flush(unsigned long start, unsigned long stop);
 
-#ifdef CONFIG_SYS_NONCACHED_MEMORY
-void noncached_init(void);
-phys_addr_t noncached_alloc(size_t size, size_t align);
-#endif /* CONFIG_SYS_NONCACHED_MEMORY */
-
 #endif /* __ASSEMBLY__ */
 
 #define arch_align_stack(x) (x)
@@ -302,6 +298,11 @@ phys_addr_t noncached_alloc(size_t size, size_t align);
 void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size,
 				     enum dcache_option option);
 
+#ifdef CONFIG_SYS_NONCACHED_MEMORY
+void noncached_init(void);
+phys_addr_t noncached_alloc(size_t size, size_t align);
+#endif /* CONFIG_SYS_NONCACHED_MEMORY */
+
 #endif /* __ASSEMBLY__ */
 
 #endif
diff --git a/arch/arm/lib/Makefile b/arch/arm/lib/Makefile
index 2bdfaba..f3db7b5 100644
--- a/arch/arm/lib/Makefile
+++ b/arch/arm/lib/Makefile
@@ -60,3 +60,27 @@ obj-$(CONFIG_DEBUG_LL)	+= debug.o
 ifneq (,$(findstring -mabi=aapcs-linux,$(PLATFORM_CPPFLAGS)))
 extra-y	+= eabi_compat.o
 endif
+
+# some files can only build in ARM or THUMB2, not THUMB1
+
+ifdef CONFIG_SYS_THUMB_BUILD
+ifndef CONFIG_HAS_THUMB2
+
+# for C files, just apend -marm, which will override previous -mthumb*
+
+CFLAGS_cache.o := -marm
+CFLAGS_cache-cp15.o := -marm
+
+# For .S, drop -mthumb* and other thumb-related options.
+# CFLAGS_REMOVE_* would not have an effet, so AFLAGS_REMOVE_*
+# was implemented and is used here.
+# Also, define ${target}_NO_THUMB_BUILD for these two targets
+# so that the code knows it should not use Thumb.
+
+AFLAGS_REMOVE_memset.o := -mthumb -mthumb-interwork
+AFLAGS_REMOVE_memcpy.o := -mthumb -mthumb-interwork
+AFLAGS_memset.o := -DMEMSET_NO_THUMB_BUILD
+AFLAGS_memcpy.o := -DMEMCPY_NO_THUMB_BUILD
+
+endif
+endif
diff --git a/arch/arm/lib/cache.c b/arch/arm/lib/cache.c
index cd13db3..3bd8710 100644
--- a/arch/arm/lib/cache.c
+++ b/arch/arm/lib/cache.c
@@ -88,3 +88,14 @@ phys_addr_t noncached_alloc(size_t size, size_t align)
 	return next;
 }
 #endif /* CONFIG_SYS_NONCACHED_MEMORY */
+
+#if defined(CONFIG_SYS_THUMB_BUILD)
+void invalidate_l2_cache(void)
+{
+	unsigned int val = 0;
+
+	asm volatile("mcr p15, 1, %0, c15, c11, 0 @ invl l2 cache"
+		: : "r" (val) : "cc");
+	isb();
+}
+#endif
diff --git a/arch/arm/lib/memcpy.S b/arch/arm/lib/memcpy.S
index eeaf003..7d9fc0f 100644
--- a/arch/arm/lib/memcpy.S
+++ b/arch/arm/lib/memcpy.S
@@ -13,7 +13,7 @@
 #include <linux/linkage.h>
 #include <asm/assembler.h>
 
-#ifdef CONFIG_SYS_THUMB_BUILD
+#if defined(CONFIG_SYS_THUMB_BUILD) && !defined(MEMCPY_NO_THUMB_BUILD)
 #define W(instr)	instr.w
 #else
 #define W(instr)	instr
@@ -62,7 +62,7 @@
 
 /* Prototype: void *memcpy(void *dest, const void *src, size_t n); */
 	.syntax unified
-#ifdef CONFIG_SYS_THUMB_BUILD
+#if defined(CONFIG_SYS_THUMB_BUILD) && !defined(MEMCPY_NO_THUMB_BUILD)
 	.thumb
 	.thumb_func
 #endif
diff --git a/arch/arm/lib/memset.S b/arch/arm/lib/memset.S
index 7208f20..df053a3 100644
--- a/arch/arm/lib/memset.S
+++ b/arch/arm/lib/memset.S
@@ -16,7 +16,7 @@
 	.align	5
 
 	.syntax unified
-#ifdef CONFIG_SYS_THUMB_BUILD
+#if defined(CONFIG_SYS_THUMB_BUILD) && !defined(MEMSET_NO_THUMB_BUILD)
 	.thumb
 	.thumb_func
 #endif
diff --git a/arch/arm/lib/semihosting.c b/arch/arm/lib/semihosting.c
index c3e964e..e32ad90 100644
--- a/arch/arm/lib/semihosting.c
+++ b/arch/arm/lib/semihosting.c
@@ -31,6 +31,8 @@ static noinline long smh_trap(unsigned int sysnum, void *addr)
 	register long result asm("r0");
 #if defined(CONFIG_ARM64)
 	asm volatile ("hlt #0xf000" : "=r" (result) : "0"(sysnum), "r"(addr));
+#elif defined(CONFIG_CPU_V7M)
+	asm volatile ("bkpt #0xAB" : "=r" (result) : "0"(sysnum), "r"(addr));
 #else
 	/* Note - untested placeholder */
 	asm volatile ("svc #0x123456" : "=r" (result) : "0"(sysnum), "r"(addr));
@@ -90,7 +92,7 @@ static long smh_read(long fd, void *memp, size_t len)
 		size_t len;
 	} read;
 
-	debug("%s: fd %ld, memp %p, len %lu\n", __func__, fd, memp, len);
+	debug("%s: fd %ld, memp %p, len %zu\n", __func__, fd, memp, len);
 
 	read.fd = fd;
 	read.memp = memp;
@@ -104,7 +106,7 @@ static long smh_read(long fd, void *memp, size_t len)
 		 * hard to maintain partial read loops and such, just fail
 		 * with an error message.
 		 */
-		printf("%s: ERROR ret %ld, fd %ld, len %lu memp %p\n",
+		printf("%s: ERROR ret %ld, fd %ld, len %zu memp %p\n",
 		       __func__, ret, fd, len, memp);
 		return -1;
 	}
diff --git a/arch/arm/mach-kirkwood/Kconfig b/arch/arm/mach-kirkwood/Kconfig
index aab5d19..f7737bf 100644
--- a/arch/arm/mach-kirkwood/Kconfig
+++ b/arch/arm/mach-kirkwood/Kconfig
@@ -4,6 +4,9 @@ choice
 	prompt "Marvell Kirkwood board select"
 	optional
 
+config TARGET_OPENRD
+	bool "Marvell OpenRD Board"
+
 config TARGET_DREAMPLUG
 	bool "DreamPlug Board"
 
@@ -51,6 +54,7 @@ endchoice
 config SYS_SOC
 	default "kirkwood"
 
+source "board/Marvell/openrd/Kconfig"
 source "board/Marvell/dreamplug/Kconfig"
 source "board/Marvell/guruplug/Kconfig"
 source "board/Marvell/sheevaplug/Kconfig"
diff --git a/arch/arm/mach-kirkwood/Makefile b/arch/arm/mach-kirkwood/Makefile
index df4756e..5abcf70 100644
--- a/arch/arm/mach-kirkwood/Makefile
+++ b/arch/arm/mach-kirkwood/Makefile
@@ -9,3 +9,9 @@
 obj-y	= cpu.o
 obj-y	+= cache.o
 obj-y	+= mpp.o
+
+# cpu.o and cache.o contain CP15 instructions which cannot be run in
+# Thumb state, so build them for ARM state even with CONFIG_SYS_THUMB_BUILD
+
+CFLAGS_cpu.o := -marm
+CFLAGS_cache.o := -marm
diff --git a/arch/arm/mach-orion5x/Makefile b/arch/arm/mach-orion5x/Makefile
index 546ebcb..33dcad4 100644
--- a/arch/arm/mach-orion5x/Makefile
+++ b/arch/arm/mach-orion5x/Makefile
@@ -16,3 +16,13 @@ obj-y	+= timer.o
 ifndef CONFIG_SKIP_LOWLEVEL_INIT
 obj-y	+= lowlevel_init.o
 endif
+
+# some files can only build in ARM or THUMB2, not THUMB1
+
+ifdef CONFIG_SYS_THUMB_BUILD
+ifndef CONFIG_HAS_THUMB2
+
+CFLAGS_cpu.o := -marm
+
+endif
+endif
diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile
index 75924ad..98431a9 100644
--- a/arch/arm/mach-tegra/Makefile
+++ b/arch/arm/mach-tegra/Makefile
@@ -15,6 +15,7 @@ obj-$(CONFIG_CMD_ENTERRCM) += cmd_enterrcm.o
 obj-$(CONFIG_PWM_TEGRA) += pwm.o
 endif
 
+obj-$(CONFIG_ARM64) += arm64-mmu.o
 obj-y += ap.o
 obj-y += board.o board2.o
 obj-y += cache.o
diff --git a/arch/arm/mach-tegra/arm64-mmu.c b/arch/arm/mach-tegra/arm64-mmu.c
new file mode 100644
index 0000000..c227652
--- /dev/null
+++ b/arch/arm/mach-tegra/arm64-mmu.c
@@ -0,0 +1,131 @@
+/*
+ * (C) Copyright 2014 - 2015 Xilinx, Inc.
+ * Michal Simek <michal.simek@xilinx.com>
+ * (This file derived from arch/arm/cpu/armv8/zynqmp/cpu.c)
+ *
+ * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/system.h>
+#include <asm/armv8/mmu.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define SECTION_SHIFT_L1	30UL
+#define SECTION_SHIFT_L2	21UL
+#define BLOCK_SIZE_L0		0x8000000000UL
+#define BLOCK_SIZE_L1		(1 << SECTION_SHIFT_L1)
+#define BLOCK_SIZE_L2		(1 << SECTION_SHIFT_L2)
+
+#define TCR_TG1_4K		(1 << 31)
+#define TCR_EPD1_DISABLE	(1 << 23)
+#define TEGRA_VA_BITS		40
+#define TEGRA_TCR		TCR_TG1_4K | \
+				TCR_EPD1_DISABLE | \
+				TCR_SHARED_OUTER | \
+				TCR_SHARED_INNER | \
+				TCR_IRGN_WBWA | \
+				TCR_ORGN_WBWA | \
+				TCR_T0SZ(TEGRA_VA_BITS)
+
+#define MEMORY_ATTR	PMD_SECT_AF | PMD_SECT_INNER_SHARE |	\
+			PMD_ATTRINDX(MT_NORMAL) |	\
+			PMD_TYPE_SECT
+#define DEVICE_ATTR	PMD_SECT_AF | PMD_SECT_PXN |	\
+			PMD_SECT_UXN | PMD_ATTRINDX(MT_DEVICE_NGNRNE) |	\
+			PMD_TYPE_SECT
+
+/* 4K size is required to place 512 entries in each level */
+#define TLB_TABLE_SIZE	0x1000
+
+/*
+ * This mmu table looks as below
+ * Level 0 table contains two entries to 512GB sizes. One is Level1 Table 0
+ * and other Level1 Table1.
+ * Level1 Table0 contains entries for each 1GB from 0 to 511GB.
+ * Level1 Table1 contains entries for each 1GB from 512GB to 1TB.
+ * Level2 Table0, Level2 Table1, Level2 Table2 and Level2 Table3 contains
+ * entries for each 2MB starting from 0GB, 1GB, 2GB and 3GB respectively.
+ */
+void mmu_setup(void)
+{
+	int el;
+	u64 i, section_l1t0, section_l1t1;
+	u64 section_l2t0, section_l2t1, section_l2t2, section_l2t3;
+	u64 *level0_table = (u64 *)gd->arch.tlb_addr;
+	u64 *level1_table_0 = (u64 *)(gd->arch.tlb_addr + TLB_TABLE_SIZE);
+	u64 *level1_table_1 = (u64 *)(gd->arch.tlb_addr + (2 * TLB_TABLE_SIZE));
+	u64 *level2_table_0 = (u64 *)(gd->arch.tlb_addr + (3 * TLB_TABLE_SIZE));
+	u64 *level2_table_1 = (u64 *)(gd->arch.tlb_addr + (4 * TLB_TABLE_SIZE));
+	u64 *level2_table_2 = (u64 *)(gd->arch.tlb_addr + (5 * TLB_TABLE_SIZE));
+	u64 *level2_table_3 = (u64 *)(gd->arch.tlb_addr + (6 * TLB_TABLE_SIZE));
+
+	/* Invalidate all table entries */
+	memset(level0_table, 0, PGTABLE_SIZE);
+
+	level0_table[0] =
+		(u64)level1_table_0 | PMD_TYPE_TABLE;
+	level0_table[1] =
+		(u64)level1_table_1 | PMD_TYPE_TABLE;
+
+	/*
+	 * set level 1 table 0, covering 0 to 512GB
+	 * set level 1 table 1, covering 512GB to 1TB
+	 */
+	section_l1t0 = 0;
+	section_l1t1 = BLOCK_SIZE_L0;
+
+	for (i = 0; i < 512; i++) {
+		level1_table_0[i] = section_l1t0;
+		if (i >= 4)
+			level1_table_0[i] |= MEMORY_ATTR;
+		level1_table_1[i] = section_l1t1;
+		level1_table_1[i] |= MEMORY_ATTR;
+		section_l1t0 += BLOCK_SIZE_L1;
+		section_l1t1 += BLOCK_SIZE_L1;
+	}
+
+	level1_table_0[0] =
+		(u64)level2_table_0 | PMD_TYPE_TABLE;
+	level1_table_0[1] =
+		(u64)level2_table_1 | PMD_TYPE_TABLE;
+	level1_table_0[2] =
+		(u64)level2_table_2 | PMD_TYPE_TABLE;
+	level1_table_0[3] =
+		(u64)level2_table_3 | PMD_TYPE_TABLE;
+
+	section_l2t0 = 0;
+	section_l2t1 = section_l2t0 + BLOCK_SIZE_L1; /* 1GB */
+	section_l2t2 = section_l2t1 + BLOCK_SIZE_L1; /* 2GB */
+	section_l2t3 = section_l2t2 + BLOCK_SIZE_L1; /* 3GB */
+
+	for (i = 0; i < 512; i++) {
+		level2_table_0[i] = section_l2t0 | DEVICE_ATTR;
+		level2_table_1[i] = section_l2t1 | DEVICE_ATTR;
+		level2_table_2[i] = section_l2t2 | MEMORY_ATTR;
+		level2_table_3[i] = section_l2t3 | MEMORY_ATTR;
+		section_l2t0 += BLOCK_SIZE_L2;
+		section_l2t1 += BLOCK_SIZE_L2;
+		section_l2t2 += BLOCK_SIZE_L2;
+		section_l2t3 += BLOCK_SIZE_L2;
+	}
+
+	/* flush new MMU table */
+	flush_dcache_range(gd->arch.tlb_addr,
+			   gd->arch.tlb_addr + gd->arch.tlb_size);
+
+	/* point TTBR to the new table */
+	el = current_el();
+	set_ttbr_tcr_mair(el, gd->arch.tlb_addr,
+			  TEGRA_TCR, MEMORY_ATTRIBUTES);
+
+	set_sctlr(get_sctlr() | CR_M);
+}
+
+u64 *arch_get_page_table(void)
+{
+	return (u64 *)(gd->arch.tlb_addr + (3 * TLB_TABLE_SIZE));
+}
diff --git a/arch/arm/thumb1/include/asm/proc-armv/system.h b/arch/arm/thumb1/include/asm/proc-armv/system.h
new file mode 100644
index 0000000..7dfbf3d
--- /dev/null
+++ b/arch/arm/thumb1/include/asm/proc-armv/system.h
@@ -0,0 +1,69 @@
+/*
+ *  Thumb-1 drop-in for the linux/include/asm-arm/proc-armv/system.h
+ *
+ *  (C) Copyright 2015
+ *  Albert ARIBAUD <albert.u.boot@aribaud.net>
+ *
+ * The original file does not build in Thumb mode. However, in U-Boot
+ * we don't use interrupt context, so we can redefine these as empty
+ * memory barriers, which makes Thumb-1 compiler happy.
+ *
+ *  SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * Use the same macro name as linux/include/asm-arm/proc-armv/system.h
+ * here, so that if the original ever gets included after us, it won't
+ * try to re-redefine anything.
+ */
+
+#ifndef __ASM_PROC_SYSTEM_H
+#define __ASM_PROC_SYSTEM_H
+
+/*
+ * Redefine all original macros with static inline functions containing
+ * a simple memory barrier, so that they produce the same instruction
+ * ordering constraints as their original counterparts.
+ * We use static inline functions rather than macros so that we can tell
+ * the compiler to not complain about unused arguments.
+ */
+
+static inline void local_irq_save(
+	unsigned long flags __attribute__((unused)))
+{
+	__asm__ __volatile__ ("" : : : "memory");
+}
+
+static inline void local_irq_enable(void)
+{
+	__asm__ __volatile__ ("" : : : "memory");
+}
+
+static inline void local_irq_disable(void)
+{
+	__asm__ __volatile__ ("" : : : "memory");
+}
+
+static inline void __stf(void)
+{
+	__asm__ __volatile__ ("" : : : "memory");
+}
+
+static inline void __clf(void)
+{
+	__asm__ __volatile__ ("" : : : "memory");
+}
+
+static inline void local_save_flags(
+	unsigned long flags __attribute__((unused)))
+{
+	__asm__ __volatile__ ("" : : : "memory");
+}
+
+static inline void local_irq_restore(
+	unsigned long flags __attribute__((unused)))
+{
+	__asm__ __volatile__ ("" : : : "memory");
+}
+
+#endif /*  __ASM_PROC_SYSTEM_H */