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| author | York Sun <york.sun@nxp.com> | 2016-11-16 11:26:45 -0800 |
|---|---|---|
| committer | York Sun <york.sun@nxp.com> | 2016-11-23 23:42:05 -0800 |
| commit | 99d0a3123e5dff47c1c4a2c541f7d53ea08d9150 (patch) | |
| tree | c53398731239358ceb8183c0310082b797012f79 /arch | |
| parent | 2f2d54b7cdeca694585f080bd4ef66b4b796f7d3 (diff) | |
| download | u-boot-imx-99d0a3123e5dff47c1c4a2c541f7d53ea08d9150.zip u-boot-imx-99d0a3123e5dff47c1c4a2c541f7d53ea08d9150.tar.gz u-boot-imx-99d0a3123e5dff47c1c4a2c541f7d53ea08d9150.tar.bz2 | |
powerpc: MPC8560: Remove macro CONFIG_MPC8560
Replace CONFIG_MPC8560 with ARCH_MPC8560 in Kconfig and clean up existing
macros.
Signed-off-by: York Sun <york.sun@nxp.com>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/powerpc/cpu/mpc85xx/Kconfig | 4 | ||||
| -rw-r--r-- | arch/powerpc/cpu/mpc85xx/cpu.c | 2 | ||||
| -rw-r--r-- | arch/powerpc/cpu/mpc85xx/speed.c | 4 | ||||
| -rw-r--r-- | arch/powerpc/include/asm/config_mpc85xx.h | 2 | ||||
| -rw-r--r-- | arch/powerpc/include/asm/fsl_lbc.h | 2 |
5 files changed, 9 insertions, 5 deletions
diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig index c58f76f..98f98af 100644 --- a/arch/powerpc/cpu/mpc85xx/Kconfig +++ b/arch/powerpc/cpu/mpc85xx/Kconfig @@ -80,6 +80,7 @@ config TARGET_MPC8555CDS config TARGET_MPC8560ADS bool "Support MPC8560ADS" + select ARCH_MPC8560 config TARGET_MPC8568MDS bool "Support MPC8568MDS" @@ -211,6 +212,9 @@ config ARCH_MPC8548 config ARCH_MPC8555 bool +config ARCH_MPC8560 + bool + source "board/freescale/b4860qds/Kconfig" source "board/freescale/bsc9131rdb/Kconfig" source "board/freescale/bsc9132qds/Kconfig" diff --git a/arch/powerpc/cpu/mpc85xx/cpu.c b/arch/powerpc/cpu/mpc85xx/cpu.c index 3e6f8f3..268429b 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu.c +++ b/arch/powerpc/cpu/mpc85xx/cpu.c @@ -294,7 +294,7 @@ int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { /* Everything after the first generation of PQ3 parts has RSTCR */ #if defined(CONFIG_ARCH_MPC8540) || defined(CONFIG_ARCH_MPC8541) || \ - defined(CONFIG_ARCH_MPC8555) || defined(CONFIG_MPC8560) + defined(CONFIG_ARCH_MPC8555) || defined(CONFIG_ARCH_MPC8560) unsigned long val, msr; /* diff --git a/arch/powerpc/cpu/mpc85xx/speed.c b/arch/powerpc/cpu/mpc85xx/speed.c index 93c7193..a7f43b6 100644 --- a/arch/powerpc/cpu/mpc85xx/speed.c +++ b/arch/powerpc/cpu/mpc85xx/speed.c @@ -626,7 +626,7 @@ void get_sys_info(sys_info_t *sys_info) */ lcrr_div *= 4; #elif !defined(CONFIG_ARCH_MPC8540) && !defined(CONFIG_ARCH_MPC8541) && \ - !defined(CONFIG_ARCH_MPC8555) && !defined(CONFIG_MPC8560) + !defined(CONFIG_ARCH_MPC8555) && !defined(CONFIG_ARCH_MPC8560) /* * Yes, the entire PQ38 family use the same * bit-representation for twice the clock divider values. @@ -682,7 +682,7 @@ int get_clocks (void) * AN2919. */ #if defined(CONFIG_ARCH_MPC8540) || defined(CONFIG_ARCH_MPC8541) || \ - defined(CONFIG_MPC8560) || defined(CONFIG_ARCH_MPC8555) || \ + defined(CONFIG_ARCH_MPC8560) || defined(CONFIG_ARCH_MPC8555) || \ defined(CONFIG_P1022) gd->arch.i2c1_clk = sys_info.freq_systembus; #elif defined(CONFIG_ARCH_MPC8544) diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index 4e38d23..ef591b9 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -92,7 +92,7 @@ #define CONFIG_SYS_FSL_SEC_COMPAT 2 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 -#elif defined(CONFIG_MPC8560) +#elif defined(CONFIG_ARCH_MPC8560) #define CONFIG_MAX_CPUS 1 #define CONFIG_SYS_FSL_NUM_LAWS 8 #define CONFIG_SYS_FSL_DDRC_GEN1 diff --git a/arch/powerpc/include/asm/fsl_lbc.h b/arch/powerpc/include/asm/fsl_lbc.h index ff9b2d9..b8270c5 100644 --- a/arch/powerpc/include/asm/fsl_lbc.h +++ b/arch/powerpc/include/asm/fsl_lbc.h @@ -327,7 +327,7 @@ void lbc_sdram_init(void); #define LCRR_CLKDIV_SHIFT 0 #if defined(CONFIG_MPC83xx) || defined(CONFIG_ARCH_MPC8540) || \ defined(CONFIG_ARCH_MPC8541) || defined(CONFIG_ARCH_MPC8555) || \ - defined(CONFIG_MPC8560) + defined(CONFIG_ARCH_MPC8560) #define LCRR_CLKDIV_2 0x00000002 #define LCRR_CLKDIV_4 0x00000004 #define LCRR_CLKDIV_8 0x00000008 |