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| author | Lokesh Vutla <lokeshvutla@ti.com> | 2016-11-03 15:32:51 +0530 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2016-11-13 15:54:36 -0500 |
| commit | 8b01ebd8128821febd84ee0f413c16d6339678d6 (patch) | |
| tree | b111512fea47f10f2aec8a421574babe36c58ab4 /arch | |
| parent | 06d43c808d61580d977526deca328e33382b40c8 (diff) | |
| download | u-boot-imx-8b01ebd8128821febd84ee0f413c16d6339678d6.zip u-boot-imx-8b01ebd8128821febd84ee0f413c16d6339678d6.tar.gz u-boot-imx-8b01ebd8128821febd84ee0f413c16d6339678d6.tar.bz2 | |
ARM: keystone2: PLL: Enable glitch free initialization sequence
Update the PLL initialization sequence to avoid glitches while
programming. User guide for the same is available at[1].
[1] http://www.ti.com/lit/ug/sprugv2h/sprugv2h.pdf
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/mach-keystone/clock.c | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/arch/arm/mach-keystone/clock.c b/arch/arm/mach-keystone/clock.c index d8804724..68f8980 100644 --- a/arch/arm/mach-keystone/clock.c +++ b/arch/arm/mach-keystone/clock.c @@ -163,15 +163,15 @@ void configure_secondary_pll(const struct pll_init_data *data) { int pllod = data->pll_od - 1; + /* Enable Glitch free bypass for ARM PLL */ + if (cpu_is_k2hk() && data->pll == TETRIS_PLL) + clrbits_le32(KS2_MISC_CTRL, MISC_CTL1_ARM_PLL_EN); + /* Enable Bypass mode */ setbits_le32(keystone_pll_regs[data->pll].reg1, CFG_PLLCTL1_ENSAT_MASK); setbits_le32(keystone_pll_regs[data->pll].reg0, CFG_PLLCTL0_BYPASS_MASK); - /* Enable Glitch free bypass for ARM PLL */ - if (cpu_is_k2hk() && data->pll == TETRIS_PLL) - clrbits_le32(KS2_MISC_CTRL, MISC_CTL1_ARM_PLL_EN); - configure_mult_div(data); /* Program Output Divider */ @@ -189,10 +189,6 @@ void configure_secondary_pll(const struct pll_init_data *data) if (data->pll == PASS_PLL && cpu_is_k2hk()) pll_pa_clk_sel(); - /* Select the Output of ARM PLL as input to ARM */ - if (data->pll == TETRIS_PLL) - setbits_le32(KS2_MISC_CTRL, MISC_CTL1_ARM_PLL_EN); - clrbits_le32(keystone_pll_regs[data->pll].reg1, CFG_PLLCTL1_RST_MASK); /* Wait for 500 * REFCLK cucles * (PLLD + 1) */ sdelay(105000); @@ -200,6 +196,10 @@ void configure_secondary_pll(const struct pll_init_data *data) /* Switch to PLL mode */ clrbits_le32(keystone_pll_regs[data->pll].reg0, CFG_PLLCTL0_BYPASS_MASK); + + /* Select the Output of ARM PLL as input to ARM */ + if (cpu_is_k2hk() && data->pll == TETRIS_PLL) + setbits_le32(KS2_MISC_CTRL, MISC_CTL1_ARM_PLL_EN); } void init_pll(const struct pll_init_data *data) |