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authorKumar Gala <galak@kernel.crashing.org>2011-03-13 10:55:53 -0500
committerKumar Gala <galak@kernel.crashing.org>2011-03-15 01:25:51 -0500
commit7afc45ad7d9493208d89072cbb78a5bfc8034b59 (patch)
tree233adc7346c3ec0f4e84cb8637ad79d9b43a5bba /arch
parentcc1dd33f273f8c96cbd7539b4a2d1d7aa12773cd (diff)
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powerpc/85xx: Fix synchronization of timebase on MP boot
There is a small ordering issue in the master core in that we need to make sure the disabling of the timebase in the SoC is visible before we set the value to 0. We can simply just read back the value to synchronizatize the write, before we set TB to 0. Reported-by: Dan Hettena Tested-by: Dan Hettena Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'arch')
-rw-r--r--arch/powerpc/cpu/mpc85xx/mp.c9
1 files changed, 9 insertions, 0 deletions
diff --git a/arch/powerpc/cpu/mpc85xx/mp.c b/arch/powerpc/cpu/mpc85xx/mp.c
index 6c0da83..758e6d7 100644
--- a/arch/powerpc/cpu/mpc85xx/mp.c
+++ b/arch/powerpc/cpu/mpc85xx/mp.c
@@ -276,8 +276,13 @@ static void plat_mp_up(unsigned long bootpg)
/* enable time base at the platform */
out_be32(&rcpm->ctbenrl, 0);
+
+ /* readback to sync write */
+ in_be32(&rcpm->ctbenrl);
+
mtspr(SPRN_TBWU, 0);
mtspr(SPRN_TBWL, 0);
+
out_be32(&rcpm->ctbenrl, (1 << nr_cpus) - 1);
#ifdef CONFIG_MPC8xxx_DISABLE_BPTR
@@ -347,6 +352,10 @@ static void plat_mp_up(unsigned long bootpg)
else
devdisr |= MPC85xx_DEVDISR_TB0;
out_be32(&gur->devdisr, devdisr);
+
+ /* readback to sync write */
+ in_be32(&gur->devdisr);
+
mtspr(SPRN_TBWU, 0);
mtspr(SPRN_TBWL, 0);