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authorWolfgang Denk <wd@denx.de>2011-01-25 21:13:04 +0100
committerWolfgang Denk <wd@denx.de>2011-01-25 21:13:04 +0100
commit5aebe3b07254d9ec8f7ae23a4525a6c535a7f858 (patch)
tree398660b7a43c39cee91c51e54678eab46aa7103d /arch
parentd6a5e6d531e357dd8016141f73d370d02886a7eb (diff)
parent92966835e96af324fed574815036e481be807d04 (diff)
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Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx
Diffstat (limited to 'arch')
-rw-r--r--arch/powerpc/cpu/mpc85xx/Makefile6
-rw-r--r--arch/powerpc/cpu/mpc85xx/cmd_errata.c3
-rw-r--r--arch/powerpc/cpu/mpc85xx/cpu.c9
-rw-r--r--arch/powerpc/cpu/mpc85xx/ddr-gen3.c99
-rw-r--r--arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c17
-rw-r--r--arch/powerpc/cpu/mpc85xx/p2040_serdes.c66
-rw-r--r--arch/powerpc/cpu/mpc85xx/p3041_ids.c105
-rw-r--r--arch/powerpc/cpu/mpc85xx/p3041_serdes.c151
-rw-r--r--arch/powerpc/cpu/mpc85xx/p5020_ids.c105
-rw-r--r--arch/powerpc/cpu/mpc85xx/p5020_serdes.c151
-rw-r--r--arch/powerpc/cpu/mpc85xx/speed.c6
-rw-r--r--arch/powerpc/cpu/mpc85xx/u-boot.lds8
-rw-r--r--arch/powerpc/cpu/mpc8xxx/cpu.c8
-rw-r--r--arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c262
-rw-r--r--arch/powerpc/cpu/mpc8xxx/ddr/ddr.h8
-rw-r--r--arch/powerpc/cpu/mpc8xxx/ddr/lc_common_dimm_params.c20
-rw-r--r--arch/powerpc/cpu/mpc8xxx/ddr/main.c31
-rw-r--r--arch/powerpc/cpu/mpc8xxx/ddr/options.c395
-rw-r--r--arch/powerpc/include/asm/config.h39
-rw-r--r--arch/powerpc/include/asm/config_mpc85xx.h188
-rw-r--r--arch/powerpc/include/asm/config_mpc86xx.h38
-rw-r--r--arch/powerpc/include/asm/fsl_ddr_sdram.h52
-rw-r--r--arch/powerpc/include/asm/immap_85xx.h23
-rw-r--r--arch/powerpc/include/asm/processor.h6
24 files changed, 1639 insertions, 157 deletions
diff --git a/arch/powerpc/cpu/mpc85xx/Makefile b/arch/powerpc/cpu/mpc85xx/Makefile
index af7bc09..b7f51e7 100644
--- a/arch/powerpc/cpu/mpc85xx/Makefile
+++ b/arch/powerpc/cpu/mpc85xx/Makefile
@@ -50,9 +50,11 @@ COBJS-$(CONFIG_MPC8544) += ddr-gen2.o
COBJS-$(CONFIG_MPC8572) += ddr-gen3.o
COBJS-$(CONFIG_MPC8536) += ddr-gen3.o
COBJS-$(CONFIG_MPC8569) += ddr-gen3.o
+COBJS-$(CONFIG_P1010) += ddr-gen3.o
COBJS-$(CONFIG_P1011) += ddr-gen3.o
COBJS-$(CONFIG_P1012) += ddr-gen3.o
COBJS-$(CONFIG_P1013) += ddr-gen3.o
+COBJS-$(CONFIG_P1014) += ddr-gen3.o
COBJS-$(CONFIG_P1020) += ddr-gen3.o
COBJS-$(CONFIG_P1021) += ddr-gen3.o
COBJS-$(CONFIG_P1022) += ddr-gen3.o
@@ -70,7 +72,9 @@ COBJS-$(CONFIG_PCI) += pci.o
COBJS-$(CONFIG_FSL_CORENET) += portals.o
# various SoC specific assignments
+COBJS-$(CONFIG_PPC_P3041) += p3041_ids.o
COBJS-$(CONFIG_PPC_P4080) += p4080_ids.o
+COBJS-$(CONFIG_PPC_P5020) += p5020_ids.o
COBJS-$(CONFIG_QE) += qe_io.o
COBJS-$(CONFIG_CPM2) += serial_scc.o
@@ -91,7 +95,9 @@ COBJS-$(CONFIG_P1021) += p1021_serdes.o
COBJS-$(CONFIG_P1022) += p1022_serdes.o
COBJS-$(CONFIG_P2010) += p2020_serdes.o
COBJS-$(CONFIG_P2020) += p2020_serdes.o
+COBJS-$(CONFIG_PPC_P3041) += p3041_serdes.o
COBJS-$(CONFIG_PPC_P4080) += p4080_serdes.o
+COBJS-$(CONFIG_PPC_P5020) += p5020_serdes.o
COBJS = $(COBJS-y)
COBJS += cpu.o
diff --git a/arch/powerpc/cpu/mpc85xx/cmd_errata.c b/arch/powerpc/cpu/mpc85xx/cmd_errata.c
index 7dfa596..0cc8b1e 100644
--- a/arch/powerpc/cpu/mpc85xx/cmd_errata.c
+++ b/arch/powerpc/cpu/mpc85xx/cmd_errata.c
@@ -68,6 +68,9 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
#ifdef CONFIG_SYS_FSL_ERRATUM_ELBC_A001
puts("Work-around for Erratum ELBC-A001 enabled\n");
#endif
+#ifdef CONFIG_SYS_FSL_ERRATUM_DDR_A003
+ puts("Work-around for Erratum DDR-A003 enabled\n");
+#endif
return 0;
}
diff --git a/arch/powerpc/cpu/mpc85xx/cpu.c b/arch/powerpc/cpu/mpc85xx/cpu.c
index 4ef9be1..1aad2ba 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu.c
@@ -1,5 +1,5 @@
/*
- * Copyright 2004,2007-2010 Freescale Semiconductor, Inc.
+ * Copyright 2004,2007-2011 Freescale Semiconductor, Inc.
* (C) Copyright 2002, 2003 Motorola Inc.
* Xianghua Xiao (X.Xiao@motorola.com)
*
@@ -166,12 +166,14 @@ int checkcpu (void)
}
#endif
+#if defined(CONFIG_FSL_LBC)
if (sysinfo.freqLocalBus > LCRR_CLKDIV) {
printf("LBC:%-4s MHz\n", strmhz(buf1, sysinfo.freqLocalBus));
} else {
printf("LBC: unknown (LCRR[CLKDIV] = 0x%02lx)\n",
sysinfo.freqLocalBus);
}
+#endif
#ifdef CONFIG_CPM2
printf("CPM: %s MHz\n", strmhz(buf1, sysinfo.freqSystemBus));
@@ -284,7 +286,10 @@ void mpc85xx_reginfo(void)
{
print_tlbcam();
print_laws();
+#if defined(CONFIG_FSL_LBC)
print_lbc_regs();
+#endif
+
}
/* Common ddr init for non-corenet fsl 85xx platforms */
@@ -330,8 +335,10 @@ phys_size_t initdram(int board_type)
ddr_enable_ecc(dram_size);
#endif
+#if defined(CONFIG_FSL_LBC)
/* Some boards also have sdram on the lbc */
lbc_sdram_init();
+#endif
puts("DDR: ");
return dram_size;
diff --git a/arch/powerpc/cpu/mpc85xx/ddr-gen3.c b/arch/powerpc/cpu/mpc85xx/ddr-gen3.c
index e46dcb7..fa7e09f 100644
--- a/arch/powerpc/cpu/mpc85xx/ddr-gen3.c
+++ b/arch/powerpc/cpu/mpc85xx/ddr-gen3.c
@@ -1,5 +1,5 @@
/*
- * Copyright 2008 Freescale Semiconductor, Inc.
+ * Copyright 2008-2011 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
@@ -9,6 +9,7 @@
#include <common.h>
#include <asm/io.h>
#include <asm/fsl_ddr_sdram.h>
+#include <asm/processor.h>
#if (CONFIG_CHIP_SELECTS_PER_CTRL > 4)
#error Invalid setting for CONFIG_CHIP_SELECTS_PER_CTRL
@@ -65,6 +66,12 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
out_be32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2);
out_be32(&ddr->sdram_mode, regs->ddr_sdram_mode);
out_be32(&ddr->sdram_mode_2, regs->ddr_sdram_mode_2);
+ out_be32(&ddr->sdram_mode_3, regs->ddr_sdram_mode_3);
+ out_be32(&ddr->sdram_mode_4, regs->ddr_sdram_mode_4);
+ out_be32(&ddr->sdram_mode_5, regs->ddr_sdram_mode_5);
+ out_be32(&ddr->sdram_mode_6, regs->ddr_sdram_mode_6);
+ out_be32(&ddr->sdram_mode_7, regs->ddr_sdram_mode_7);
+ out_be32(&ddr->sdram_mode_8, regs->ddr_sdram_mode_8);
out_be32(&ddr->sdram_md_cntl, regs->ddr_sdram_md_cntl);
out_be32(&ddr->sdram_interval, regs->ddr_sdram_interval);
out_be32(&ddr->sdram_data_init, regs->ddr_data_init);
@@ -79,11 +86,93 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
out_be32(&ddr->ddr_sr_cntr, regs->ddr_sr_cntr);
out_be32(&ddr->ddr_sdram_rcw_1, regs->ddr_sdram_rcw_1);
out_be32(&ddr->ddr_sdram_rcw_2, regs->ddr_sdram_rcw_2);
+ out_be32(&ddr->ddr_cdr1, regs->ddr_cdr1);
+ out_be32(&ddr->ddr_cdr2, regs->ddr_cdr2);
+ out_be32(&ddr->err_disable, regs->err_disable);
+ out_be32(&ddr->err_int_en, regs->err_int_en);
+ for (i = 0; i < 32; i++)
+ out_be32(&ddr->debug[i], regs->debug[i]);
/* Set, but do not enable the memory */
temp_sdram_cfg = regs->ddr_sdram_cfg;
temp_sdram_cfg &= ~(SDRAM_CFG_MEM_EN);
out_be32(&ddr->sdram_cfg, temp_sdram_cfg);
+#ifdef CONFIG_SYS_FSL_ERRATUM_DDR_A003
+ if (regs->ddr_sdram_rcw_2 & 0x00f00000) {
+ out_be32(&ddr->timing_cfg_2, regs->timing_cfg_2 & 0xf07fffff);
+ out_be32(&ddr->debug[2], 0x00000400);
+ out_be32(&ddr->ddr_zq_cntl, regs->ddr_zq_cntl & 0x7fffffff);
+ out_be32(&ddr->ddr_wrlvl_cntl, regs->ddr_wrlvl_cntl & 0x7fffffff);
+ out_be32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2 & 0xffffffeb);
+ out_be32(&ddr->mtcr, 0);
+ out_be32(&ddr->debug[12], 0x00000015);
+ out_be32(&ddr->debug[21], 0x24000000);
+ out_be32(&ddr->sdram_interval, regs->ddr_sdram_interval & 0xffff);
+ out_be32(&ddr->sdram_cfg, temp_sdram_cfg | SDRAM_CFG_BI | SDRAM_CFG_MEM_EN);
+
+ asm volatile("sync;isync");
+ while (!(in_be32(&ddr->debug[1]) & 0x2))
+ ;
+
+ switch (regs->ddr_sdram_rcw_2 & 0x00f00000) {
+ case 0x00000000:
+ out_be32(&ddr->sdram_md_cntl,
+ MD_CNTL_MD_EN |
+ MD_CNTL_CS_SEL_CS0_CS1 |
+ 0x04000000 |
+ MD_CNTL_WRCW |
+ MD_CNTL_MD_VALUE(0x02));
+ break;
+ case 0x00100000:
+ out_be32(&ddr->sdram_md_cntl,
+ MD_CNTL_MD_EN |
+ MD_CNTL_CS_SEL_CS0_CS1 |
+ 0x04000000 |
+ MD_CNTL_WRCW |
+ MD_CNTL_MD_VALUE(0x0a));
+ break;
+ case 0x00200000:
+ out_be32(&ddr->sdram_md_cntl,
+ MD_CNTL_MD_EN |
+ MD_CNTL_CS_SEL_CS0_CS1 |
+ 0x04000000 |
+ MD_CNTL_WRCW |
+ MD_CNTL_MD_VALUE(0x12));
+ break;
+ case 0x00300000:
+ out_be32(&ddr->sdram_md_cntl,
+ MD_CNTL_MD_EN |
+ MD_CNTL_CS_SEL_CS0_CS1 |
+ 0x04000000 |
+ MD_CNTL_WRCW |
+ MD_CNTL_MD_VALUE(0x1a));
+ break;
+ default:
+ out_be32(&ddr->sdram_md_cntl,
+ MD_CNTL_MD_EN |
+ MD_CNTL_CS_SEL_CS0_CS1 |
+ 0x04000000 |
+ MD_CNTL_WRCW |
+ MD_CNTL_MD_VALUE(0x02));
+ printf("Unsupported RC10\n");
+ break;
+ }
+
+ while (in_be32(&ddr->sdram_md_cntl) & 0x80000000)
+ ;
+ udelay(6);
+ out_be32(&ddr->sdram_cfg, temp_sdram_cfg);
+ out_be32(&ddr->timing_cfg_2, regs->timing_cfg_2);
+ out_be32(&ddr->debug[2], 0x0);
+ out_be32(&ddr->ddr_zq_cntl, regs->ddr_zq_cntl);
+ out_be32(&ddr->ddr_wrlvl_cntl, regs->ddr_wrlvl_cntl);
+ out_be32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2);
+ out_be32(&ddr->debug[12], 0x0);
+ out_be32(&ddr->debug[21], 0x0);
+ out_be32(&ddr->sdram_interval, regs->ddr_sdram_interval);
+
+ }
+#endif
/*
* For 8572 DDR1 erratum - DDR controller may enter illegal state
* when operatiing in 32-bit bus mode with 4-beat bursts,
@@ -93,8 +182,7 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
if ((((in_be32(&ddr->sdram_cfg) >> 24) & 0x7) == SDRAM_TYPE_DDR2)
&& in_be32(&ddr->sdram_cfg) & 0x80000) {
/* set DEBUG_1[31] */
- u32 temp = in_be32(&ddr->debug_1);
- out_be32(&ddr->debug_1, temp | 1);
+ setbits_be32(&ddr->debug[0], 1);
}
#endif
@@ -108,8 +196,11 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
asm volatile("sync;isync");
/* Let the controller go */
- temp_sdram_cfg = in_be32(&ddr->sdram_cfg);
+ temp_sdram_cfg = in_be32(&ddr->sdram_cfg) & ~SDRAM_CFG_BI;
out_be32(&ddr->sdram_cfg, temp_sdram_cfg | SDRAM_CFG_MEM_EN);
+ asm volatile("sync;isync");
+ while (!(in_be32(&ddr->debug[1]) & 0x2))
+ ;
/* Poll DDR_SDRAM_CFG_2[D_INIT] bit until auto-data init is done. */
while (in_be32(&ddr->sdram_cfg_2) & 0x10) {
diff --git a/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c b/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c
index 5bcf91a..7fc00d8 100644
--- a/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c
+++ b/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c
@@ -1,5 +1,5 @@
/*
- * Copyright 2009-2010 Freescale Semiconductor, Inc.
+ * Copyright 2009-2011 Freescale Semiconductor, Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
@@ -33,6 +33,8 @@
static u32 serdes_prtcl_map;
+#define HWCONFIG_BUFFER_SIZE 128
+
#ifdef DEBUG
static const char *serdes_prtcl_str[] = {
[NONE] = "NA",
@@ -277,6 +279,15 @@ void fsl_serdes_init(void)
const char *srds_lpd_arg;
size_t arglen;
#endif
+ char buffer[HWCONFIG_BUFFER_SIZE];
+ char *buf = NULL;
+
+ /*
+ * Extract hwconfig from environment since we have not properly setup
+ * the environment but need it for ddr config params
+ */
+ if (getenv_f("hwconfig", buffer, sizeof(buffer)) > 0)
+ buf = buffer;
/* Is serdes enabled at all? */
if (!(in_be32(&gur->rcwsr[5]) & FSL_CORENET_RCWSR5_SRDS_EN))
@@ -295,8 +306,8 @@ void fsl_serdes_init(void)
if (!IS_SVR_REV(get_svr(), 1, 0))
for (bank = 1; bank < ARRAY_SIZE(srds_lpd_b); bank++) {
sprintf(srds_lpd_opt, "fsl_srds_lpd_b%u", bank + 1);
- srds_lpd_arg = hwconfig_subarg("serdes", srds_lpd_opt,
- &arglen);
+ srds_lpd_arg = hwconfig_subarg_f("serdes", srds_lpd_opt,
+ &arglen, buf);
if (srds_lpd_arg)
srds_lpd_b[bank] = simple_strtoul(srds_lpd_arg,
NULL, 0);
diff --git a/arch/powerpc/cpu/mpc85xx/p2040_serdes.c b/arch/powerpc/cpu/mpc85xx/p2040_serdes.c
new file mode 100644
index 0000000..a96eff4
--- /dev/null
+++ b/arch/powerpc/cpu/mpc85xx/p2040_serdes.c
@@ -0,0 +1,66 @@
+/*
+ * Copyright 2010-2011 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/fsl_serdes.h>
+#include <asm/processor.h>
+#include <asm/io.h>
+#include "fsl_corenet_serdes.h"
+
+static u8 serdes_cfg_tbl[][SRDS_MAX_LANES] = {
+ [0x2] = {NONE, NONE, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1,
+ NONE, NONE, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
+ SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, NONE, NONE, NONE, NONE, },
+ [0x5] = {NONE, NONE, PCIE1, PCIE3, PCIE2, PCIE2, PCIE2, PCIE2,
+ NONE, NONE, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
+ SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, NONE, NONE, NONE, NONE, },
+ [0x8] = {NONE, NONE, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, PCIE2,
+ PCIE2, PCIE2, PCIE2, NONE, NONE, NONE, NONE, SATA1,
+ SATA2, NONE, NONE, NONE, NONE, },
+ [0xa] = {NONE, NONE, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, PCIE2,
+ PCIE2, PCIE2, PCIE2, NONE, NONE, PCIE3, PCIE3, PCIE3,
+ PCIE3, NONE, NONE, NONE, NONE, },
+ [0xf] = {NONE, NONE, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, SRIO2,
+ SRIO2, SRIO1, SRIO1, NONE, NONE, PCIE3, SGMII_FM1_DTSEC5,
+ SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, NONE, NONE, NONE, NONE, },
+ [0x14] = {NONE, NONE, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, PCIE2,
+ PCIE2, SRIO1, SRIO1, NONE, NONE, AURORA,
+ SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, NONE,
+ NONE, NONE, NONE, },
+ [0x16] = {NONE, NONE, PCIE1, PCIE3, PCIE2, PCIE2, SGMII_FM1_DTSEC3,
+ SGMII_FM1_DTSEC4, NONE, NONE, NONE, NONE, SATA1, SATA2, NONE,
+ NONE, NONE, NONE, },
+ [0x1a] = {NONE, NONE, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, SRIO2,
+ SRIO2, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, NONE, NONE,
+ NONE, NONE, SATA1, SATA2, NONE, NONE, NONE, NONE, },
+ [0x1c] = {NONE, NONE, PCIE1, SGMII_FM1_DTSEC2, PCIE2, PCIE2,
+ SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, NONE, NONE, AURORA,
+ SGMII_FM1_DTSEC5, NONE, NONE, NONE, NONE, NONE, NONE, },
+};
+
+enum srds_prtcl serdes_get_prtcl(int cfg, int lane)
+{
+ if (!serdes_lane_enabled(lane))
+ return NONE;
+
+ return serdes_cfg_tbl[cfg][lane];
+}
diff --git a/arch/powerpc/cpu/mpc85xx/p3041_ids.c b/arch/powerpc/cpu/mpc85xx/p3041_ids.c
new file mode 100644
index 0000000..febbee9
--- /dev/null
+++ b/arch/powerpc/cpu/mpc85xx/p3041_ids.c
@@ -0,0 +1,105 @@
+/*
+ * Copyright 2010 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/fsl_portals.h>
+#include <asm/fsl_liodn.h>
+
+struct qportal_info qp_info[CONFIG_SYS_QMAN_NUM_PORTALS] = {
+ /* dqrr liodn, frame data liodn, liodn off, sdest */
+ SET_QP_INFO( 1, 2, 1, 0),
+ SET_QP_INFO( 3, 4, 2, 1),
+ SET_QP_INFO( 5, 6, 3, 2),
+ SET_QP_INFO( 7, 8, 4, 3),
+ SET_QP_INFO( 9, 10, 5, 4),
+ SET_QP_INFO( 0, 0, 0, 5),
+ SET_QP_INFO( 0, 0, 0, 6),
+ SET_QP_INFO( 0, 0, 0, 7),
+ SET_QP_INFO( 0, 0, 0, 0), /* for now sdest to 0 */
+ SET_QP_INFO( 0, 0, 0, 0), /* for now sdest to 0 */
+};
+
+struct liodn_id_table liodn_tbl[] = {
+ SET_QMAN_LIODN(31),
+ SET_BMAN_LIODN(32),
+
+ SET_SDHC_LIODN(1, 64),
+
+ SET_PME_LIODN(117),
+
+ SET_USB_LIODN(1, "fsl-usb2-mph", 125),
+ SET_USB_LIODN(2, "fsl-usb2-dr", 126),
+
+ SET_SATA_LIODN(1, 127),
+ SET_SATA_LIODN(2, 128),
+
+ SET_PCI_LIODN(1, 193),
+ SET_PCI_LIODN(2, 194),
+ SET_PCI_LIODN(3, 195),
+ SET_PCI_LIODN(4, 196),
+
+ SET_DMA_LIODN(1, 197),
+ SET_DMA_LIODN(2, 198),
+
+ SET_GUTS_LIODN("fsl,rapidio-delta", 199, rio1liodnr, 0),
+ SET_GUTS_LIODN(NULL, 200, rio2liodnr, 0),
+ SET_GUTS_LIODN(NULL, 201, rio1maintliodnr, 0),
+ SET_GUTS_LIODN(NULL, 202, rio2maintliodnr, 0),
+};
+
+#ifdef CONFIG_SYS_DPAA_FMAN
+struct liodn_id_table fman1_liodn_tbl[] = {
+ SET_FMAN_RX_1G_LIODN(1, 0, 10),
+ SET_FMAN_RX_1G_LIODN(1, 1, 11),
+ SET_FMAN_RX_1G_LIODN(1, 2, 12),
+ SET_FMAN_RX_1G_LIODN(1, 3, 13),
+ SET_FMAN_RX_1G_LIODN(1, 4, 14),
+ SET_FMAN_RX_10G_LIODN(1, 0, 15),
+};
+#endif
+
+struct liodn_id_table sec_liodn_tbl[] = {
+ SET_SEC_JR_LIODN_ENTRY(0, 129, 130),
+ SET_SEC_JR_LIODN_ENTRY(1, 131, 132),
+ SET_SEC_JR_LIODN_ENTRY(2, 133, 134),
+ SET_SEC_JR_LIODN_ENTRY(3, 135, 136),
+ SET_SEC_RTIC_LIODN_ENTRY(a, 154),
+ SET_SEC_RTIC_LIODN_ENTRY(b, 155),
+ SET_SEC_RTIC_LIODN_ENTRY(c, 156),
+ SET_SEC_RTIC_LIODN_ENTRY(d, 157),
+ SET_SEC_DECO_LIODN_ENTRY(0, 97, 98),
+ SET_SEC_DECO_LIODN_ENTRY(1, 99, 100),
+};
+
+struct liodn_id_table liodn_bases[] = {
+ [FSL_HW_PORTAL_SEC] = SET_LIODN_BASE_2(64, 100),
+#ifdef CONFIG_SYS_DPAA_FMAN
+ [FSL_HW_PORTAL_FMAN1] = SET_LIODN_BASE_1(32),
+#endif
+#ifdef CONFIG_SYS_DPAA_PME
+ [FSL_HW_PORTAL_PME] = SET_LIODN_BASE_2(136, 172),
+#endif
+};
+
+int liodn_tbl_sz = ARRAY_SIZE(liodn_tbl);
+int fman1_liodn_tbl_sz = ARRAY_SIZE(fman1_liodn_tbl);
+int sec_liodn_tbl_sz = ARRAY_SIZE(sec_liodn_tbl);
diff --git a/arch/powerpc/cpu/mpc85xx/p3041_serdes.c b/arch/powerpc/cpu/mpc85xx/p3041_serdes.c
new file mode 100644
index 0000000..fba9ff2
--- /dev/null
+++ b/arch/powerpc/cpu/mpc85xx/p3041_serdes.c
@@ -0,0 +1,151 @@
+/*
+ * Copyright 2009-2011 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/fsl_serdes.h>
+#include <asm/processor.h>
+#include <asm/io.h>
+#include "fsl_corenet_serdes.h"
+
+static u8 serdes_cfg_tbl[][SRDS_MAX_LANES] = {
+ [0x2] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2,
+ PCIE4, AURORA, PCIE3, SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC3,
+ SGMII_FM1_DTSEC4, NONE, NONE, SATA1, SATA2, },
+ [0x4] = {SRIO2, SRIO2, SRIO2, SRIO2, SRIO1, SRIO1, SRIO1, SRIO1,
+ PCIE2, AURORA, PCIE3, SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC3,
+ SGMII_FM1_DTSEC4, XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1, },
+ [0xb] = {PCIE1, PCIE1, PCIE1, PCIE1, SRIO2, SRIO2, SRIO1, SRIO1,
+ PCIE2, AURORA, PCIE3, SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC3,
+ SGMII_FM1_DTSEC4, NONE, NONE, SATA1, SATA2, },
+ [0x10] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1,
+ AURORA, AURORA, XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1,
+ NONE, NONE, SATA1, SATA2, },
+ [0x11] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2,
+ AURORA, AURORA, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
+ SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, NONE, NONE, SATA1, SATA2, },
+ [0x13] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2,
+ AURORA, AURORA, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
+ SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, XAUI_FM1, XAUI_FM1,
+ XAUI_FM1, XAUI_FM1, },
+ [0x14] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2,
+ AURORA, AURORA, PCIE3, PCIE3, PCIE3, PCIE3,
+ SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC3,
+ SGMII_FM1_DTSEC4, },
+ [0x15] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2,
+ AURORA, AURORA, XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1,
+ NONE, NONE, SATA1, SATA2, },
+ [0x16] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2,
+ AURORA, AURORA, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
+ SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, SRIO1, SRIO1, SRIO1,
+ SRIO1, },
+ [0x17] = {SRIO2, SRIO2, SRIO2, SRIO2, SRIO1, SRIO1, SRIO1, SRIO1,
+ AURORA, AURORA, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
+ SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, NONE, NONE, SATA1, SATA2, },
+ [0x18] = {SRIO2, SRIO2, SRIO2, SRIO2, SRIO1, SRIO1, SRIO1, SRIO1,
+ AURORA, AURORA, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
+ SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, SGMII_FM1_DTSEC5, NONE,
+ NONE, NONE, },
+ [0x1b] = {SRIO2, SRIO2, SRIO2, SRIO2, SRIO1, SRIO1, SRIO1, SRIO1,
+ AURORA, AURORA, XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1,
+ NONE, NONE, SATA1, SATA2, },
+ [0x1d] = {SRIO2, SRIO2, SRIO2, SRIO2, SRIO1, SRIO1, SRIO1, SRIO1,
+ AURORA, AURORA, PCIE3, PCIE3, PCIE3, PCIE3, NONE, NONE,
+ SATA1, SATA2, },
+ [0x20] = {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1,
+ AURORA, AURORA, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
+ SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, XAUI_FM1, XAUI_FM1,
+ XAUI_FM1, XAUI_FM1, },
+ [0x21] = {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1,
+ AURORA, AURORA, PCIE3, PCIE3, PCIE3, PCIE3,
+ SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC3,
+ SGMII_FM1_DTSEC4, },
+ [0x22] = {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1,
+ AURORA, AURORA, XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1,
+ NONE, NONE, SATA1, SATA2, },
+ [0x23] = {PCIE1, PCIE1, PCIE1, PCIE1, SRIO2, SRIO2, SRIO1, SRIO1,
+ AURORA, AURORA, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
+ SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, NONE, NONE, SATA1, SATA2, },
+ [0x24] = {PCIE1, PCIE1, PCIE1, PCIE1, SRIO2, SRIO2, SRIO1, SRIO1,
+ AURORA, AURORA, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
+ SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, SGMII_FM1_DTSEC5, NONE,
+ NONE, NONE, },
+ [0x28] = {PCIE1, PCIE1, PCIE3, PCIE3, PCIE2, PCIE2, PCIE2, PCIE2,
+ AURORA, AURORA, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
+ SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, NONE, NONE, SATA1, SATA2, },
+ [0x29] = {PCIE1, PCIE1, PCIE3, PCIE3, PCIE2, PCIE2, PCIE2, PCIE2,
+ AURORA, AURORA, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
+ SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, SGMII_FM1_DTSEC5, NONE,
+ NONE, NONE, },
+ [0x2a] = {PCIE1, PCIE1, PCIE3, PCIE3, PCIE2, PCIE2, PCIE2, PCIE2,
+ AURORA, AURORA, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
+ SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, XAUI_FM1, XAUI_FM1,
+ XAUI_FM1, XAUI_FM1, },
+ [0x2b] = {PCIE1, PCIE1, PCIE3, PCIE3, PCIE2, PCIE2, PCIE2, PCIE2,
+ AURORA, AURORA, XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1,
+ NONE, NONE, SATA1, SATA2, },
+ [0x2f] = {PCIE1, PCIE1, PCIE3, PCIE3, SRIO2, SRIO2, SRIO1, SRIO1,
+ AURORA, AURORA, XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1,
+ NONE, NONE, SATA1, SATA2, },
+ [0x31] = {PCIE1, PCIE1, PCIE3, PCIE3, SRIO1, SRIO1, SRIO1, SRIO1,
+ AURORA, AURORA, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
+ SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, SGMII_FM1_DTSEC5, NONE,
+ NONE, NONE, },
+ [0x33] = {PCIE1, PCIE1, PCIE3, PCIE3, SRIO1, SRIO1, SRIO1, SRIO1,
+ AURORA, AURORA, XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1,
+ NONE, NONE, SATA1, SATA2, },
+ [0x34] = {PCIE1, PCIE1, PCIE1, PCIE1, SGMII_FM1_DTSEC1,
+ SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, AURORA,
+ AURORA, XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1, NONE,
+ NONE, SATA1, SATA2, },
+ [0x35] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2,
+ SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, AURORA, AURORA, XAUI_FM1,
+ XAUI_FM1, XAUI_FM1, XAUI_FM1, NONE, NONE, SATA1, SATA2, },
+ [0x36] = {PCIE1, PCIE1, PCIE3, PCIE3, SGMII_FM1_DTSEC1,
+ SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, AURORA,
+ AURORA, XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1, NONE,
+ NONE, SATA1, SATA2, },
+ [0x37] = {PCIE1, PCIE1, PCIE3, PCIE3, PCIE2, PCIE2,
+ SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, AURORA, AURORA, XAUI_FM1,
+ XAUI_FM1, XAUI_FM1, XAUI_FM1, NONE, NONE, SATA1, SATA2, },
+};
+
+enum srds_prtcl serdes_get_prtcl(int cfg, int lane)
+{
+ if (!serdes_lane_enabled(lane))
+ return NONE;
+
+ return serdes_cfg_tbl[cfg][lane];
+}
+
+int is_serdes_prtcl_valid(u32 prtcl) {
+ int i;
+
+ if (prtcl > ARRAY_SIZE(serdes_cfg_tbl))
+ return 0;
+
+ for (i = 0; i < SRDS_MAX_LANES; i++) {
+ if (serdes_cfg_tbl[prtcl][i] != NONE)
+ return 1;
+ }
+
+ return 0;
+}
diff --git a/arch/powerpc/cpu/mpc85xx/p5020_ids.c b/arch/powerpc/cpu/mpc85xx/p5020_ids.c
new file mode 100644
index 0000000..febbee9
--- /dev/null
+++ b/arch/powerpc/cpu/mpc85xx/p5020_ids.c
@@ -0,0 +1,105 @@
+/*
+ * Copyright 2010 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/fsl_portals.h>
+#include <asm/fsl_liodn.h>
+
+struct qportal_info qp_info[CONFIG_SYS_QMAN_NUM_PORTALS] = {
+ /* dqrr liodn, frame data liodn, liodn off, sdest */
+ SET_QP_INFO( 1, 2, 1, 0),
+ SET_QP_INFO( 3, 4, 2, 1),
+ SET_QP_INFO( 5, 6, 3, 2),
+ SET_QP_INFO( 7, 8, 4, 3),
+ SET_QP_INFO( 9, 10, 5, 4),
+ SET_QP_INFO( 0, 0, 0, 5),
+ SET_QP_INFO( 0, 0, 0, 6),
+ SET_QP_INFO( 0, 0, 0, 7),
+ SET_QP_INFO( 0, 0, 0, 0), /* for now sdest to 0 */
+ SET_QP_INFO( 0, 0, 0, 0), /* for now sdest to 0 */
+};
+
+struct liodn_id_table liodn_tbl[] = {
+ SET_QMAN_LIODN(31),
+ SET_BMAN_LIODN(32),
+
+ SET_SDHC_LIODN(1, 64),
+
+ SET_PME_LIODN(117),
+
+ SET_USB_LIODN(1, "fsl-usb2-mph", 125),
+ SET_USB_LIODN(2, "fsl-usb2-dr", 126),
+
+ SET_SATA_LIODN(1, 127),
+ SET_SATA_LIODN(2, 128),
+
+ SET_PCI_LIODN(1, 193),
+ SET_PCI_LIODN(2, 194),
+ SET_PCI_LIODN(3, 195),
+ SET_PCI_LIODN(4, 196),
+
+ SET_DMA_LIODN(1, 197),
+ SET_DMA_LIODN(2, 198),
+
+ SET_GUTS_LIODN("fsl,rapidio-delta", 199, rio1liodnr, 0),
+ SET_GUTS_LIODN(NULL, 200, rio2liodnr, 0),
+ SET_GUTS_LIODN(NULL, 201, rio1maintliodnr, 0),
+ SET_GUTS_LIODN(NULL, 202, rio2maintliodnr, 0),
+};
+
+#ifdef CONFIG_SYS_DPAA_FMAN
+struct liodn_id_table fman1_liodn_tbl[] = {
+ SET_FMAN_RX_1G_LIODN(1, 0, 10),
+ SET_FMAN_RX_1G_LIODN(1, 1, 11),
+ SET_FMAN_RX_1G_LIODN(1, 2, 12),
+ SET_FMAN_RX_1G_LIODN(1, 3, 13),
+ SET_FMAN_RX_1G_LIODN(1, 4, 14),
+ SET_FMAN_RX_10G_LIODN(1, 0, 15),
+};
+#endif
+
+struct liodn_id_table sec_liodn_tbl[] = {
+ SET_SEC_JR_LIODN_ENTRY(0, 129, 130),
+ SET_SEC_JR_LIODN_ENTRY(1, 131, 132),
+ SET_SEC_JR_LIODN_ENTRY(2, 133, 134),
+ SET_SEC_JR_LIODN_ENTRY(3, 135, 136),
+ SET_SEC_RTIC_LIODN_ENTRY(a, 154),
+ SET_SEC_RTIC_LIODN_ENTRY(b, 155),
+ SET_SEC_RTIC_LIODN_ENTRY(c, 156),
+ SET_SEC_RTIC_LIODN_ENTRY(d, 157),
+ SET_SEC_DECO_LIODN_ENTRY(0, 97, 98),
+ SET_SEC_DECO_LIODN_ENTRY(1, 99, 100),
+};
+
+struct liodn_id_table liodn_bases[] = {
+ [FSL_HW_PORTAL_SEC] = SET_LIODN_BASE_2(64, 100),
+#ifdef CONFIG_SYS_DPAA_FMAN
+ [FSL_HW_PORTAL_FMAN1] = SET_LIODN_BASE_1(32),
+#endif
+#ifdef CONFIG_SYS_DPAA_PME
+ [FSL_HW_PORTAL_PME] = SET_LIODN_BASE_2(136, 172),
+#endif
+};
+
+int liodn_tbl_sz = ARRAY_SIZE(liodn_tbl);
+int fman1_liodn_tbl_sz = ARRAY_SIZE(fman1_liodn_tbl);
+int sec_liodn_tbl_sz = ARRAY_SIZE(sec_liodn_tbl);
diff --git a/arch/powerpc/cpu/mpc85xx/p5020_serdes.c b/arch/powerpc/cpu/mpc85xx/p5020_serdes.c
new file mode 100644
index 0000000..fba9ff2
--- /dev/null
+++ b/arch/powerpc/cpu/mpc85xx/p5020_serdes.c
@@ -0,0 +1,151 @@
+/*
+ * Copyright 2009-2011 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/fsl_serdes.h>
+#include <asm/processor.h>
+#include <asm/io.h>
+#include "fsl_corenet_serdes.h"
+
+static u8 serdes_cfg_tbl[][SRDS_MAX_LANES] = {
+ [0x2] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2,
+ PCIE4, AURORA, PCIE3, SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC3,
+ SGMII_FM1_DTSEC4, NONE, NONE, SATA1, SATA2, },
+ [0x4] = {SRIO2, SRIO2, SRIO2, SRIO2, SRIO1, SRIO1, SRIO1, SRIO1,
+ PCIE2, AURORA, PCIE3, SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC3,
+ SGMII_FM1_DTSEC4, XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1, },
+ [0xb] = {PCIE1, PCIE1, PCIE1, PCIE1, SRIO2, SRIO2, SRIO1, SRIO1,
+ PCIE2, AURORA, PCIE3, SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC3,
+ SGMII_FM1_DTSEC4, NONE, NONE, SATA1, SATA2, },
+ [0x10] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1,
+ AURORA, AURORA, XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1,
+ NONE, NONE, SATA1, SATA2, },
+ [0x11] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2,
+ AURORA, AURORA, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
+ SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, NONE, NONE, SATA1, SATA2, },
+ [0x13] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2,
+ AURORA, AURORA, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
+ SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, XAUI_FM1, XAUI_FM1,
+ XAUI_FM1, XAUI_FM1, },
+ [0x14] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2,
+ AURORA, AURORA, PCIE3, PCIE3, PCIE3, PCIE3,
+ SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC3,
+ SGMII_FM1_DTSEC4, },
+ [0x15] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2,
+ AURORA, AURORA, XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1,
+ NONE, NONE, SATA1, SATA2, },
+ [0x16] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2,
+ AURORA, AURORA, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
+ SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, SRIO1, SRIO1, SRIO1,
+ SRIO1, },
+ [0x17] = {SRIO2, SRIO2, SRIO2, SRIO2, SRIO1, SRIO1, SRIO1, SRIO1,
+ AURORA, AURORA, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
+ SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, NONE, NONE, SATA1, SATA2, },
+ [0x18] = {SRIO2, SRIO2, SRIO2, SRIO2, SRIO1, SRIO1, SRIO1, SRIO1,
+ AURORA, AURORA, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
+ SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, SGMII_FM1_DTSEC5, NONE,
+ NONE, NONE, },
+ [0x1b] = {SRIO2, SRIO2, SRIO2, SRIO2, SRIO1, SRIO1, SRIO1, SRIO1,
+ AURORA, AURORA, XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1,
+ NONE, NONE, SATA1, SATA2, },
+ [0x1d] = {SRIO2, SRIO2, SRIO2, SRIO2, SRIO1, SRIO1, SRIO1, SRIO1,
+ AURORA, AURORA, PCIE3, PCIE3, PCIE3, PCIE3, NONE, NONE,
+ SATA1, SATA2, },
+ [0x20] = {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1,
+ AURORA, AURORA, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
+ SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, XAUI_FM1, XAUI_FM1,
+ XAUI_FM1, XAUI_FM1, },
+ [0x21] = {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1,
+ AURORA, AURORA, PCIE3, PCIE3, PCIE3, PCIE3,
+ SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC3,
+ SGMII_FM1_DTSEC4, },
+ [0x22] = {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1,
+ AURORA, AURORA, XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1,
+ NONE, NONE, SATA1, SATA2, },
+ [0x23] = {PCIE1, PCIE1, PCIE1, PCIE1, SRIO2, SRIO2, SRIO1, SRIO1,
+ AURORA, AURORA, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
+ SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, NONE, NONE, SATA1, SATA2, },
+ [0x24] = {PCIE1, PCIE1, PCIE1, PCIE1, SRIO2, SRIO2, SRIO1, SRIO1,
+ AURORA, AURORA, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
+ SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, SGMII_FM1_DTSEC5, NONE,
+ NONE, NONE, },
+ [0x28] = {PCIE1, PCIE1, PCIE3, PCIE3, PCIE2, PCIE2, PCIE2, PCIE2,
+ AURORA, AURORA, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
+ SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, NONE, NONE, SATA1, SATA2, },
+ [0x29] = {PCIE1, PCIE1, PCIE3, PCIE3, PCIE2, PCIE2, PCIE2, PCIE2,
+ AURORA, AURORA, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
+ SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, SGMII_FM1_DTSEC5, NONE,
+ NONE, NONE, },
+ [0x2a] = {PCIE1, PCIE1, PCIE3, PCIE3, PCIE2, PCIE2, PCIE2, PCIE2,
+ AURORA, AURORA, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
+ SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, XAUI_FM1, XAUI_FM1,
+ XAUI_FM1, XAUI_FM1, },
+ [0x2b] = {PCIE1, PCIE1, PCIE3, PCIE3, PCIE2, PCIE2, PCIE2, PCIE2,
+ AURORA, AURORA, XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1,
+ NONE, NONE, SATA1, SATA2, },
+ [0x2f] = {PCIE1, PCIE1, PCIE3, PCIE3, SRIO2, SRIO2, SRIO1, SRIO1,
+ AURORA, AURORA, XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1,
+ NONE, NONE, SATA1, SATA2, },
+ [0x31] = {PCIE1, PCIE1, PCIE3, PCIE3, SRIO1, SRIO1, SRIO1, SRIO1,
+ AURORA, AURORA, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
+ SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, SGMII_FM1_DTSEC5, NONE,
+ NONE, NONE, },
+ [0x33] = {PCIE1, PCIE1, PCIE3, PCIE3, SRIO1, SRIO1, SRIO1, SRIO1,
+ AURORA, AURORA, XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1,
+ NONE, NONE, SATA1, SATA2, },
+ [0x34] = {PCIE1, PCIE1, PCIE1, PCIE1, SGMII_FM1_DTSEC1,
+ SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, AURORA,
+ AURORA, XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1, NONE,
+ NONE, SATA1, SATA2, },
+ [0x35] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2,
+ SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, AURORA, AURORA, XAUI_FM1,
+ XAUI_FM1, XAUI_FM1, XAUI_FM1, NONE, NONE, SATA1, SATA2, },
+ [0x36] = {PCIE1, PCIE1, PCIE3, PCIE3, SGMII_FM1_DTSEC1,
+ SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, AURORA,
+ AURORA, XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1, NONE,
+ NONE, SATA1, SATA2, },
+ [0x37] = {PCIE1, PCIE1, PCIE3, PCIE3, PCIE2, PCIE2,
+ SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, AURORA, AURORA, XAUI_FM1,
+ XAUI_FM1, XAUI_FM1, XAUI_FM1, NONE, NONE, SATA1, SATA2, },
+};
+
+enum srds_prtcl serdes_get_prtcl(int cfg, int lane)
+{
+ if (!serdes_lane_enabled(lane))
+ return NONE;
+
+ return serdes_cfg_tbl[cfg][lane];
+}
+
+int is_serdes_prtcl_valid(u32 prtcl) {
+ int i;
+
+ if (prtcl > ARRAY_SIZE(serdes_cfg_tbl))
+ return 0;
+
+ for (i = 0; i < SRDS_MAX_LANES; i++) {
+ if (serdes_cfg_tbl[prtcl][i] != NONE)
+ return 1;
+ }
+
+ return 0;
+}
diff --git a/arch/powerpc/cpu/mpc85xx/speed.c b/arch/powerpc/cpu/mpc85xx/speed.c
index dd4c6b3..f2aa8d0 100644
--- a/arch/powerpc/cpu/mpc85xx/speed.c
+++ b/arch/powerpc/cpu/mpc85xx/speed.c
@@ -1,5 +1,5 @@
/*
- * Copyright 2004, 2007-2010 Freescale Semiconductor, Inc.
+ * Copyright 2004, 2007-2011 Freescale Semiconductor, Inc.
*
* (C) Copyright 2003 Motorola Inc.
* Xianghua Xiao, (X.Xiao@motorola.com)
@@ -131,7 +131,9 @@ void get_sys_info (sys_info_t * sysInfo)
#else
uint plat_ratio,e500_ratio,half_freqSystemBus;
+#if defined(CONFIG_FSL_LBC)
uint lcrr_div;
+#endif
int i;
#ifdef CONFIG_QE
u32 qe_ratio;
@@ -168,6 +170,7 @@ void get_sys_info (sys_info_t * sysInfo)
sysInfo->freqQE = qe_ratio * CONFIG_SYS_CLK_FREQ;
#endif
+#if defined(CONFIG_FSL_LBC)
#if defined(CONFIG_SYS_LBC_LCRR)
/* We will program LCRR to this value later */
lcrr_div = CONFIG_SYS_LBC_LCRR & LCRR_CLKDIV;
@@ -193,6 +196,7 @@ void get_sys_info (sys_info_t * sysInfo)
/* In case anyone cares what the unknown value is */
sysInfo->freqLocalBus = lcrr_div;
}
+#endif
}
diff --git a/arch/powerpc/cpu/mpc85xx/u-boot.lds b/arch/powerpc/cpu/mpc85xx/u-boot.lds
index 67d7763..506c7f2 100644
--- a/arch/powerpc/cpu/mpc85xx/u-boot.lds
+++ b/arch/powerpc/cpu/mpc85xx/u-boot.lds
@@ -1,5 +1,5 @@
/*
- * Copyright 2007-2009 Freescale Semiconductor, Inc.
+ * Copyright 2007-2009, 2011 Freescale Semiconductor, Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
@@ -20,7 +20,11 @@
* MA 02111-1307 USA
*/
-#ifndef RESET_VECTOR_ADDRESS
+#include "config.h" /* CONFIG_BOARDDIR */
+
+#ifdef CONFIG_RESET_VECTOR_ADDRESS
+#define RESET_VECTOR_ADDRESS CONFIG_RESET_VECTOR_ADDRESS
+#else
#define RESET_VECTOR_ADDRESS 0xfffffffc
#endif
diff --git a/arch/powerpc/cpu/mpc8xxx/cpu.c b/arch/powerpc/cpu/mpc8xxx/cpu.c
index 5b30fbd..4335fb4 100644
--- a/arch/powerpc/cpu/mpc8xxx/cpu.c
+++ b/arch/powerpc/cpu/mpc8xxx/cpu.c
@@ -1,5 +1,5 @@
/*
- * Copyright 2009-2010 Freescale Semiconductor, Inc.
+ * Copyright 2009-2011 Freescale Semiconductor, Inc.
*
* This file is derived from arch/powerpc/cpu/mpc85xx/cpu.c and
* arch/powerpc/cpu/mpc86xx/cpu.c. Basically this file contains
@@ -64,11 +64,15 @@ struct cpu_type cpu_type_list [] = {
CPU_TYPE_ENTRY(8569, 8569_E, 1),
CPU_TYPE_ENTRY(8572, 8572, 2),
CPU_TYPE_ENTRY(8572, 8572_E, 2),
+ CPU_TYPE_ENTRY(P1010, P1010, 1),
+ CPU_TYPE_ENTRY(P1010, P1010_E, 1),
CPU_TYPE_ENTRY(P1011, P1011, 1),
CPU_TYPE_ENTRY(P1011, P1011_E, 1),
CPU_TYPE_ENTRY(P1012, P1012, 1),
CPU_TYPE_ENTRY(P1012, P1012_E, 1),
CPU_TYPE_ENTRY(P1013, P1013, 1),
+ CPU_TYPE_ENTRY(P1014, P1014_E, 1),
+ CPU_TYPE_ENTRY(P1014, P1014, 1),
CPU_TYPE_ENTRY(P1013, P1013_E, 1),
CPU_TYPE_ENTRY(P1020, P1020, 2),
CPU_TYPE_ENTRY(P1020, P1020_E, 2),
@@ -80,6 +84,8 @@ struct cpu_type cpu_type_list [] = {
CPU_TYPE_ENTRY(P2010, P2010_E, 1),
CPU_TYPE_ENTRY(P2020, P2020, 2),
CPU_TYPE_ENTRY(P2020, P2020_E, 2),
+ CPU_TYPE_ENTRY(P2040, P2040, 4),
+ CPU_TYPE_ENTRY(P2040, P2040_E, 4),
CPU_TYPE_ENTRY(P3041, P3041, 4),
CPU_TYPE_ENTRY(P3041, P3041_E, 4),
CPU_TYPE_ENTRY(P4040, P4040, 4),
diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c b/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c
index 3fec100..c3e1d76 100644
--- a/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c
+++ b/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c
@@ -1,5 +1,5 @@
/*
- * Copyright 2008-2010 Freescale Semiconductor, Inc.
+ * Copyright 2008-2011 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the Free
@@ -18,7 +18,28 @@
#include "ddr.h"
-extern unsigned int picos_to_mclk(unsigned int picos);
+#ifdef CONFIG_MPC85xx
+ #define _DDR_ADDR CONFIG_SYS_MPC85xx_DDR_ADDR
+#elif defined(CONFIG_MPC86xx)
+ #define _DDR_ADDR CONFIG_SYS_MPC86xx_DDR_ADDR
+#else
+ #error "Undefined _DDR_ADDR"
+#endif
+
+u32 fsl_ddr_get_version(void)
+{
+ ccsr_ddr_t *ddr;
+ u32 ver_major_minor_errata;
+
+ ddr = (void *)_DDR_ADDR;
+ ver_major_minor_errata = (in_be32(&ddr->ip_rev1) & 0xFFFF) << 8;
+ ver_major_minor_errata |= (in_be32(&ddr->ip_rev2) & 0xFF00) >> 8;
+
+ return ver_major_minor_errata;
+}
+
+unsigned int picos_to_mclk(unsigned int picos);
+
/*
* Determine Rtt value.
*
@@ -187,7 +208,8 @@ static void set_csn_config_2(int i, fsl_ddr_cfg_regs_t *ddr)
* Avoid writing for DDR I. The new PQ38 DDR controller
* dreams up non-zero default values to be backwards compatible.
*/
-static void set_timing_cfg_0(fsl_ddr_cfg_regs_t *ddr)
+static void set_timing_cfg_0(fsl_ddr_cfg_regs_t *ddr,
+ const memctl_options_t *popts)
{
unsigned char trwt_mclk = 0; /* Read-to-write turnaround */
unsigned char twrt_mclk = 0; /* Write-to-read turnaround */
@@ -204,7 +226,7 @@ static void set_timing_cfg_0(fsl_ddr_cfg_regs_t *ddr)
/* Mode register set cycle time (tMRD). */
unsigned char tmrd_mclk;
-#if defined(CONFIG_FSL_DDR3)
+#ifdef CONFIG_FSL_DDR3
/*
* (tXARD and tXARDS). Empirical?
* The DDR3 spec has not tXARD,
@@ -214,13 +236,21 @@ static void set_timing_cfg_0(fsl_ddr_cfg_regs_t *ddr)
* tAXPD=1, need design to confirm.
*/
int tXP = max((get_memory_clk_period_ps() * 3), 7500); /* unit=ps */
- act_pd_exit_mclk = picos_to_mclk(tXP);
- /* Mode register MR0[A12] is '1' - fast exit */
- pre_pd_exit_mclk = act_pd_exit_mclk;
- taxpd_mclk = 1;
tmrd_mclk = 4;
/* set the turnaround time */
trwt_mclk = 1;
+
+ if (popts->dynamic_power == 0) { /* powerdown is not used */
+ act_pd_exit_mclk = 1;
+ pre_pd_exit_mclk = 1;
+ taxpd_mclk = 1;
+ } else {
+ /* act_pd_exit_mclk = tXARD, see above */
+ act_pd_exit_mclk = picos_to_mclk(tXP);
+ /* Mode register MR0[A12] is '1' - fast exit */
+ pre_pd_exit_mclk = act_pd_exit_mclk;
+ taxpd_mclk = 1;
+ }
#else /* CONFIG_FSL_DDR2 */
/*
* (tXARD and tXARDS). Empirical?
@@ -450,28 +480,34 @@ static void set_timing_cfg_2(fsl_ddr_cfg_regs_t *ddr,
/* DDR SDRAM Register Control Word */
static void set_ddr_sdram_rcw(fsl_ddr_cfg_regs_t *ddr,
+ const memctl_options_t *popts,
const common_timing_params_t *common_dimm)
{
if (common_dimm->all_DIMMs_registered
&& !common_dimm->all_DIMMs_unbuffered) {
- ddr->ddr_sdram_rcw_1 =
- common_dimm->rcw[0] << 28 | \
- common_dimm->rcw[1] << 24 | \
- common_dimm->rcw[2] << 20 | \
- common_dimm->rcw[3] << 16 | \
- common_dimm->rcw[4] << 12 | \
- common_dimm->rcw[5] << 8 | \
- common_dimm->rcw[6] << 4 | \
- common_dimm->rcw[7];
- ddr->ddr_sdram_rcw_2 =
- common_dimm->rcw[8] << 28 | \
- common_dimm->rcw[9] << 24 | \
- common_dimm->rcw[10] << 20 | \
- common_dimm->rcw[11] << 16 | \
- common_dimm->rcw[12] << 12 | \
- common_dimm->rcw[13] << 8 | \
- common_dimm->rcw[14] << 4 | \
- common_dimm->rcw[15];
+ if (popts->rcw_override) {
+ ddr->ddr_sdram_rcw_1 = popts->rcw_1;
+ ddr->ddr_sdram_rcw_2 = popts->rcw_2;
+ } else {
+ ddr->ddr_sdram_rcw_1 =
+ common_dimm->rcw[0] << 28 | \
+ common_dimm->rcw[1] << 24 | \
+ common_dimm->rcw[2] << 20 | \
+ common_dimm->rcw[3] << 16 | \
+ common_dimm->rcw[4] << 12 | \
+ common_dimm->rcw[5] << 8 | \
+ common_dimm->rcw[6] << 4 | \
+ common_dimm->rcw[7];
+ ddr->ddr_sdram_rcw_2 =
+ common_dimm->rcw[8] << 28 | \
+ common_dimm->rcw[9] << 24 | \
+ common_dimm->rcw[10] << 20 | \
+ common_dimm->rcw[11] << 16 | \
+ common_dimm->rcw[12] << 12 | \
+ common_dimm->rcw[13] << 8 | \
+ common_dimm->rcw[14] << 4 | \
+ common_dimm->rcw[15];
+ }
debug("FSLDDR: ddr_sdram_rcw_1 = 0x%08x\n", ddr->ddr_sdram_rcw_1);
debug("FSLDDR: ddr_sdram_rcw_2 = 0x%08x\n", ddr->ddr_sdram_rcw_2);
}
@@ -509,8 +545,14 @@ static void set_ddr_sdram_cfg(fsl_ddr_cfg_regs_t *ddr,
ecc_en = 0;
}
- rd_en = (common_dimm->all_DIMMs_registered
- && !common_dimm->all_DIMMs_unbuffered);
+ if (common_dimm->all_DIMMs_registered
+ && !common_dimm->all_DIMMs_unbuffered) {
+ rd_en = 1;
+ twoT_en = 0;
+ } else {
+ rd_en = 0;
+ twoT_en = popts->twoT_en;
+ }
sdram_type = CONFIG_FSL_SDRAM_TYPE;
@@ -530,7 +572,6 @@ static void set_ddr_sdram_cfg(fsl_ddr_cfg_regs_t *ddr,
}
threeT_en = popts->threeT_en;
- twoT_en = popts->twoT_en;
ba_intlv_ctl = popts->ba_intlv_ctl;
hse = popts->half_strength_driver_enable;
@@ -558,7 +599,8 @@ static void set_ddr_sdram_cfg(fsl_ddr_cfg_regs_t *ddr,
/* DDR SDRAM control configuration 2 (DDR_SDRAM_CFG_2) */
static void set_ddr_sdram_cfg_2(fsl_ddr_cfg_regs_t *ddr,
- const memctl_options_t *popts)
+ const memctl_options_t *popts,
+ const unsigned int unq_mrs_en)
{
unsigned int frc_sr = 0; /* Force self refresh */
unsigned int sr_ie = 0; /* Self-refresh interrupt enable */
@@ -598,11 +640,17 @@ static void set_ddr_sdram_cfg_2(fsl_ddr_cfg_regs_t *ddr,
obc_cfg = 0;
#endif
- ap_en = 0; /* Make this configurable? */
+ if (popts->registered_dimm_en) {
+ rcw_en = 1;
+ ap_en = popts->ap_en;
+ } else {
+ rcw_en = 0;
+ ap_en = 0;
+ }
#if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
/* Use the DDR controller to auto initialize memory. */
- d_init = 1;
+ d_init = popts->ECC_init_using_memctl;
ddr->ddr_data_init = CONFIG_MEM_INIT_VALUE;
debug("DDR: ddr_data_init = 0x%08x\n", ddr->ddr_data_init);
#else
@@ -613,7 +661,6 @@ static void set_ddr_sdram_cfg_2(fsl_ddr_cfg_regs_t *ddr,
#if defined(CONFIG_FSL_DDR3)
md_en = popts->mirrored_dimm;
#endif
- rcw_en = popts->registered_dimm_en;
qd_en = popts->quad_rank_present ? 1 : 0;
ddr->ddr_sdram_cfg_2 = (0
| ((frc_sr & 0x1) << 31)
@@ -623,6 +670,7 @@ static void set_ddr_sdram_cfg_2(fsl_ddr_cfg_regs_t *ddr,
| ((odt_cfg & 0x3) << 21)
| ((num_pr & 0xf) << 12)
| (qd_en << 9)
+ | (unq_mrs_en << 8)
| ((obc_cfg & 0x1) << 6)
| ((ap_en & 0x1) << 5)
| ((d_init & 0x1) << 4)
@@ -634,12 +682,14 @@ static void set_ddr_sdram_cfg_2(fsl_ddr_cfg_regs_t *ddr,
/* DDR SDRAM Mode configuration 2 (DDR_SDRAM_MODE_2) */
static void set_ddr_sdram_mode_2(fsl_ddr_cfg_regs_t *ddr,
- const memctl_options_t *popts)
+ const memctl_options_t *popts,
+ const unsigned int unq_mrs_en)
{
unsigned short esdmode2 = 0; /* Extended SDRAM mode 2 */
unsigned short esdmode3 = 0; /* Extended SDRAM mode 3 */
#if defined(CONFIG_FSL_DDR3)
+ int i;
unsigned int rtt_wr = 0; /* Rtt_WR - dynamic ODT off */
unsigned int srt = 0; /* self-refresh temerature, normal range */
unsigned int asr = 0; /* auto self-refresh disable */
@@ -648,7 +698,8 @@ static void set_ddr_sdram_mode_2(fsl_ddr_cfg_regs_t *ddr,
if (popts->rtt_override)
rtt_wr = popts->rtt_wr_override_value;
-
+ else
+ rtt_wr = popts->cs_local_opts[0].odt_rtt_wr;
esdmode2 = (0
| ((rtt_wr & 0x3) << 9)
| ((srt & 0x1) << 7)
@@ -661,6 +712,46 @@ static void set_ddr_sdram_mode_2(fsl_ddr_cfg_regs_t *ddr,
| ((esdmode3 & 0xFFFF) << 0)
);
debug("FSLDDR: ddr_sdram_mode_2 = 0x%08x\n", ddr->ddr_sdram_mode_2);
+
+#ifdef CONFIG_FSL_DDR3
+ if (unq_mrs_en) { /* unique mode registers are supported */
+ for (i = 1; i < 4; i++) {
+ if (popts->rtt_override)
+ rtt_wr = popts->rtt_wr_override_value;
+ else
+ rtt_wr = popts->cs_local_opts[i].odt_rtt_wr;
+
+ esdmode2 &= 0xF9FF; /* clear bit 10, 9 */
+ esdmode2 |= (rtt_wr & 0x3) << 9;
+ switch (i) {
+ case 1:
+ ddr->ddr_sdram_mode_4 = (0
+ | ((esdmode2 & 0xFFFF) << 16)
+ | ((esdmode3 & 0xFFFF) << 0)
+ );
+ break;
+ case 2:
+ ddr->ddr_sdram_mode_6 = (0
+ | ((esdmode2 & 0xFFFF) << 16)
+ | ((esdmode3 & 0xFFFF) << 0)
+ );
+ break;
+ case 3:
+ ddr->ddr_sdram_mode_8 = (0
+ | ((esdmode2 & 0xFFFF) << 16)
+ | ((esdmode3 & 0xFFFF) << 0)
+ );
+ break;
+ }
+ }
+ debug("FSLDDR: ddr_sdram_mode_4 = 0x%08x\n",
+ ddr->ddr_sdram_mode_4);
+ debug("FSLDDR: ddr_sdram_mode_6 = 0x%08x\n",
+ ddr->ddr_sdram_mode_6);
+ debug("FSLDDR: ddr_sdram_mode_8 = 0x%08x\n",
+ ddr->ddr_sdram_mode_8);
+ }
+#endif
}
/* DDR SDRAM Interval Configuration (DDR_SDRAM_INTERVAL) */
@@ -689,7 +780,8 @@ static void set_ddr_sdram_mode(fsl_ddr_cfg_regs_t *ddr,
const memctl_options_t *popts,
const common_timing_params_t *common_dimm,
unsigned int cas_latency,
- unsigned int additive_latency)
+ unsigned int additive_latency,
+ const unsigned int unq_mrs_en)
{
unsigned short esdmode; /* Extended SDRAM mode */
unsigned short sdmode; /* SDRAM mode */
@@ -700,7 +792,7 @@ static void set_ddr_sdram_mode(fsl_ddr_cfg_regs_t *ddr,
unsigned int rtt;
unsigned int wrlvl_en = 0; /* Write level enable: 0=no, 1=yes */
unsigned int al = 0; /* Posted CAS# additive latency (AL) */
- unsigned int dic = 1; /* Output driver impedance, 34ohm */
+ unsigned int dic = 0; /* Output driver impedance, 40ohm */
unsigned int dll_en = 0; /* DLL Enable 0=Enable (Normal),
1=Disable (Test/Debug) */
@@ -717,16 +809,21 @@ static void set_ddr_sdram_mode(fsl_ddr_cfg_regs_t *ddr,
unsigned int wr_mclk;
const unsigned int mclk_ps = get_memory_clk_period_ps();
+ int i;
- rtt = fsl_ddr_get_rtt();
if (popts->rtt_override)
rtt = popts->rtt_override_value;
+ else
+ rtt = popts->cs_local_opts[0].odt_rtt_norm;
if (additive_latency == (cas_latency - 1))
al = 1;
if (additive_latency == (cas_latency - 2))
al = 2;
+ if (popts->quad_rank_present)
+ dic = 1; /* output driver impedance 240/7 ohm */
+
/*
* The esdmode value will also be used for writing
* MR1 during write leveling for DDR3, although the
@@ -812,6 +909,48 @@ static void set_ddr_sdram_mode(fsl_ddr_cfg_regs_t *ddr,
);
debug("FSLDDR: ddr_sdram_mode = 0x%08x\n", ddr->ddr_sdram_mode);
+
+ if (unq_mrs_en) { /* unique mode registers are supported */
+ for (i = 1; i < 4; i++) {
+ if (popts->rtt_override)
+ rtt = popts->rtt_override_value;
+ else
+ rtt = popts->cs_local_opts[i].odt_rtt_norm;
+
+ esdmode &= 0xFDBB; /* clear bit 9,6,2 */
+ esdmode |= (0
+ | ((rtt & 0x4) << 7) /* rtt field is split */
+ | ((rtt & 0x2) << 5) /* rtt field is split */
+ | ((rtt & 0x1) << 2) /* rtt field is split */
+ );
+ switch (i) {
+ case 1:
+ ddr->ddr_sdram_mode_3 = (0
+ | ((esdmode & 0xFFFF) << 16)
+ | ((sdmode & 0xFFFF) << 0)
+ );
+ break;
+ case 2:
+ ddr->ddr_sdram_mode_5 = (0
+ | ((esdmode & 0xFFFF) << 16)
+ | ((sdmode & 0xFFFF) << 0)
+ );
+ break;
+ case 3:
+ ddr->ddr_sdram_mode_7 = (0
+ | ((esdmode & 0xFFFF) << 16)
+ | ((sdmode & 0xFFFF) << 0)
+ );
+ break;
+ }
+ }
+ debug("FSLDDR: ddr_sdram_mode_3 = 0x%08x\n",
+ ddr->ddr_sdram_mode_3);
+ debug("FSLDDR: ddr_sdram_mode_5 = 0x%08x\n",
+ ddr->ddr_sdram_mode_5);
+ debug("FSLDDR: ddr_sdram_mode_5 = 0x%08x\n",
+ ddr->ddr_sdram_mode_5);
+ }
}
#else /* !CONFIG_FSL_DDR3 */
@@ -821,7 +960,8 @@ static void set_ddr_sdram_mode(fsl_ddr_cfg_regs_t *ddr,
const memctl_options_t *popts,
const common_timing_params_t *common_dimm,
unsigned int cas_latency,
- unsigned int additive_latency)
+ unsigned int additive_latency,
+ const unsigned int unq_mrs_en)
{
unsigned short esdmode; /* Extended SDRAM mode */
unsigned short sdmode; /* SDRAM mode */
@@ -1024,7 +1164,7 @@ static void set_timing_cfg_4(fsl_ddr_cfg_regs_t *ddr,
}
/* DDR SDRAM Timing Configuration 5 (TIMING_CFG_5) */
-static void set_timing_cfg_5(fsl_ddr_cfg_regs_t *ddr)
+static void set_timing_cfg_5(fsl_ddr_cfg_regs_t *ddr, unsigned int cas_latency)
{
unsigned int rodt_on = 0; /* Read to ODT on */
unsigned int rodt_off = 0; /* Read to ODT off */
@@ -1032,7 +1172,8 @@ static void set_timing_cfg_5(fsl_ddr_cfg_regs_t *ddr)
unsigned int wodt_off = 0; /* Write to ODT off */
#if defined(CONFIG_FSL_DDR3)
- rodt_on = 2; /* 2 clocks */
+ /* rodt_on = timing_cfg_1[caslat] - timing_cfg_2[wrlat] + 1 */
+ rodt_on = cas_latency - ((ddr->timing_cfg_2 & 0x00780000) >> 19) + 1;
rodt_off = 4; /* 4 clocks */
wodt_on = 1; /* 1 clocks */
wodt_off = 4; /* 4 clocks */
@@ -1068,6 +1209,7 @@ static void set_ddr_zq_cntl(fsl_ddr_cfg_regs_t *ddr, unsigned int zq_en)
| ((zqoper & 0xF) << 16)
| ((zqcs & 0xF) << 8)
);
+ debug("FSLDDR: zq_cntl = 0x%08x\n", ddr->ddr_zq_cntl);
}
/* DDR Write Leveling Control (DDR_WRLVL_CNTL) */
@@ -1113,7 +1255,8 @@ static void set_ddr_wrlvl_cntl(fsl_ddr_cfg_regs_t *ddr, unsigned int wrlvl_en,
/*
* Write leveling start time
* The value use for the DQS_ADJUST for the first sample
- * when write leveling is enabled.
+ * when write leveling is enabled. It probably needs to be
+ * overriden per platform.
*/
wrlvl_start = 0x8;
/*
@@ -1135,6 +1278,7 @@ static void set_ddr_wrlvl_cntl(fsl_ddr_cfg_regs_t *ddr, unsigned int wrlvl_en,
| ((wrlvl_wlr & 0x7) << 8)
| ((wrlvl_start & 0x1F) << 0)
);
+ debug("FSLDDR: wrlvl_cntl = 0x%08x\n", ddr->ddr_wrlvl_cntl);
}
/* DDR Self Refresh Counter (DDR_SR_CNTR) */
@@ -1152,6 +1296,12 @@ static void set_ddr_eor(fsl_ddr_cfg_regs_t *ddr, const memctl_options_t *popts)
}
}
+static void set_ddr_cdr1(fsl_ddr_cfg_regs_t *ddr, const memctl_options_t *popts)
+{
+ ddr->ddr_cdr1 = popts->ddr_cdr1;
+ debug("FSLDDR: ddr_cdr1 = 0x%08x\n", ddr->ddr_cdr1);
+}
+
unsigned int
check_fsl_memctl_config_regs(const fsl_ddr_cfg_regs_t *ddr)
{
@@ -1176,7 +1326,8 @@ compute_fsl_memctl_config_regs(const memctl_options_t *popts,
fsl_ddr_cfg_regs_t *ddr,
const common_timing_params_t *common_dimm,
const dimm_params_t *dimm_params,
- unsigned int dbw_cap_adj)
+ unsigned int dbw_cap_adj,
+ unsigned int size_only)
{
unsigned int i;
unsigned int cas_latency;
@@ -1184,6 +1335,8 @@ compute_fsl_memctl_config_regs(const memctl_options_t *popts,
unsigned int sr_it;
unsigned int zq_en;
unsigned int wrlvl_en;
+ unsigned int ip_rev = 0;
+ unsigned int unq_mrs_en = 0;
int cs_en = 1;
memset(ddr, 0, sizeof(fsl_ddr_cfg_regs_t));
@@ -1394,10 +1547,17 @@ compute_fsl_memctl_config_regs(const memctl_options_t *popts,
printf("CS%d is disabled.\n", i);
}
+ /*
+ * In the case we only need to compute the ddr sdram size, we only need
+ * to set csn registers, so return from here.
+ */
+ if (size_only)
+ return 0;
+
set_ddr_eor(ddr, popts);
#if !defined(CONFIG_FSL_DDR1)
- set_timing_cfg_0(ddr);
+ set_timing_cfg_0(ddr, popts);
#endif
set_timing_cfg_3(ddr, common_dimm, cas_latency);
@@ -1405,26 +1565,30 @@ compute_fsl_memctl_config_regs(const memctl_options_t *popts,
set_timing_cfg_2(ddr, popts, common_dimm,
cas_latency, additive_latency);
+ set_ddr_cdr1(ddr, popts);
set_ddr_sdram_cfg(ddr, popts, common_dimm);
+ ip_rev = fsl_ddr_get_version();
+ if (ip_rev > 0x40400)
+ unq_mrs_en = 1;
- set_ddr_sdram_cfg_2(ddr, popts);
+ set_ddr_sdram_cfg_2(ddr, popts, unq_mrs_en);
set_ddr_sdram_mode(ddr, popts, common_dimm,
- cas_latency, additive_latency);
- set_ddr_sdram_mode_2(ddr, popts);
+ cas_latency, additive_latency, unq_mrs_en);
+ set_ddr_sdram_mode_2(ddr, popts, unq_mrs_en);
set_ddr_sdram_interval(ddr, popts, common_dimm);
set_ddr_data_init(ddr);
set_ddr_sdram_clk_cntl(ddr, popts);
set_ddr_init_addr(ddr);
set_ddr_init_ext_addr(ddr);
set_timing_cfg_4(ddr, popts);
- set_timing_cfg_5(ddr);
+ set_timing_cfg_5(ddr, cas_latency);
set_ddr_zq_cntl(ddr, zq_en);
set_ddr_wrlvl_cntl(ddr, wrlvl_en, popts);
set_ddr_sr_cntr(ddr, sr_it);
- set_ddr_sdram_rcw(ddr, common_dimm);
+ set_ddr_sdram_rcw(ddr, popts, common_dimm);
return check_fsl_memctl_config_regs(ddr);
}
diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/ddr.h b/arch/powerpc/cpu/mpc8xxx/ddr/ddr.h
index 98acb8d..35b60a0 100644
--- a/arch/powerpc/cpu/mpc8xxx/ddr/ddr.h
+++ b/arch/powerpc/cpu/mpc8xxx/ddr/ddr.h
@@ -1,5 +1,5 @@
/*
- * Copyright 2008 Freescale Semiconductor, Inc.
+ * Copyright 2008-2011 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
@@ -55,7 +55,8 @@ typedef struct {
#define STEP_ALL 0xFFF
extern unsigned long long
-fsl_ddr_compute(fsl_ddr_info_t *pinfo, unsigned int start_step);
+fsl_ddr_compute(fsl_ddr_info_t *pinfo, unsigned int start_step,
+ unsigned int size_only);
extern const char * step_to_string(unsigned int step);
@@ -64,7 +65,8 @@ compute_fsl_memctl_config_regs(const memctl_options_t *popts,
fsl_ddr_cfg_regs_t *ddr,
const common_timing_params_t *common_dimm,
const dimm_params_t *dimm_parameters,
- unsigned int dbw_capacity_adjust);
+ unsigned int dbw_capacity_adjust,
+ unsigned int size_only);
extern unsigned int
compute_lowest_common_dimm_parameters(const dimm_params_t *dimm_params,
common_timing_params_t *outpdimm,
diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/lc_common_dimm_params.c b/arch/powerpc/cpu/mpc8xxx/ddr/lc_common_dimm_params.c
index 029e566..a58e5a9 100644
--- a/arch/powerpc/cpu/mpc8xxx/ddr/lc_common_dimm_params.c
+++ b/arch/powerpc/cpu/mpc8xxx/ddr/lc_common_dimm_params.c
@@ -1,5 +1,5 @@
/*
- * Copyright 2008 Freescale Semiconductor, Inc.
+ * Copyright 2008-2011 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
@@ -98,7 +98,7 @@ compute_lowest_common_dimm_parameters(const dimm_params_t *dimm_params,
unsigned int tDQSQ_max_ps = 0;
unsigned int tQHS_ps = 0;
- unsigned int temp1, temp2, temp3;
+ unsigned int temp1, temp2;
unsigned int additive_latency = 0;
#if !defined(CONFIG_FSL_DDR3)
const unsigned int mclk_ps = get_memory_clk_period_ps();
@@ -215,18 +215,14 @@ compute_lowest_common_dimm_parameters(const dimm_params_t *dimm_params,
}
outpdimm->all_DIMMs_registered = 0;
+ outpdimm->all_DIMMs_unbuffered = 0;
if (temp1 && !temp2) {
outpdimm->all_DIMMs_registered = 1;
- }
-
- outpdimm->all_DIMMs_unbuffered = 0;
- if (!temp1 && temp2) {
+ printf("Detected RDIMM(s)\n");
+ } else if (!temp1 && temp2) {
outpdimm->all_DIMMs_unbuffered = 1;
- }
-
- /* CHECKME: */
- if (!outpdimm->all_DIMMs_registered
- && !outpdimm->all_DIMMs_unbuffered) {
+ printf("Detected UDIMM(s)\n");
+ } else {
printf("ERROR: Mix of registered buffered and unbuffered "
"DIMMs detected!\n");
}
@@ -237,7 +233,7 @@ compute_lowest_common_dimm_parameters(const dimm_params_t *dimm_params,
outpdimm->rcw[j] = dimm_params[0].rcw[j];
for (i = 1; i < number_of_dimms; i++)
if (dimm_params[i].rcw[j] != dimm_params[0].rcw[j]) {
- temp3 = 1;
+ temp1 = 1;
break;
}
}
diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/main.c b/arch/powerpc/cpu/mpc8xxx/ddr/main.c
index e3888ff..bb96d66 100644
--- a/arch/powerpc/cpu/mpc8xxx/ddr/main.c
+++ b/arch/powerpc/cpu/mpc8xxx/ddr/main.c
@@ -1,5 +1,5 @@
/*
- * Copyright 2008 Freescale Semiconductor, Inc.
+ * Copyright 2008-2011 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
@@ -233,7 +233,8 @@ int step_assign_addresses(fsl_ddr_info_t *pinfo,
}
unsigned long long
-fsl_ddr_compute(fsl_ddr_info_t *pinfo, unsigned int start_step)
+fsl_ddr_compute(fsl_ddr_info_t *pinfo, unsigned int start_step,
+ unsigned int size_only)
{
unsigned int i, j;
unsigned int all_controllers_memctl_interleaving = 0;
@@ -338,7 +339,8 @@ fsl_ddr_compute(fsl_ddr_info_t *pinfo, unsigned int start_step)
&pinfo->memctl_opts[i],
&ddr_reg[i], &timing_params[i],
pinfo->dimm_params[i],
- dbw_capacity_adjust[i]);
+ dbw_capacity_adjust[i],
+ size_only);
}
default:
@@ -405,7 +407,7 @@ phys_size_t fsl_ddr_sdram(void)
memset(&info, 0, sizeof(fsl_ddr_info_t));
/* Compute it once normally. */
- total_memory = fsl_ddr_compute(&info, STEP_GET_SPD);
+ total_memory = fsl_ddr_compute(&info, STEP_GET_SPD, 0);
/* Check for memory controller interleaving. */
memctl_interleaved = 0;
@@ -430,7 +432,8 @@ phys_size_t fsl_ddr_sdram(void)
info.memctl_opts[i].memctl_interleaving = 0;
debug("Recomputing with memctl_interleaving off.\n");
total_memory = fsl_ddr_compute(&info,
- STEP_ASSIGN_ADDRESSES);
+ STEP_ASSIGN_ADDRESSES,
+ 0);
}
}
@@ -478,3 +481,21 @@ phys_size_t fsl_ddr_sdram(void)
return total_memory;
}
+
+/*
+ * fsl_ddr_sdram_size() - This function only returns the size of the total
+ * memory without setting ddr control registers.
+ */
+phys_size_t
+fsl_ddr_sdram_size(void)
+{
+ fsl_ddr_info_t info;
+ unsigned long long total_memory = 0;
+
+ memset(&info, 0 , sizeof(fsl_ddr_info_t));
+
+ /* Compute it once normally. */
+ total_memory = fsl_ddr_compute(&info, STEP_GET_SPD, 1);
+
+ return total_memory;
+}
diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/options.c b/arch/powerpc/cpu/mpc8xxx/ddr/options.c
index c641e85..6ccc3b0 100644
--- a/arch/powerpc/cpu/mpc8xxx/ddr/options.c
+++ b/arch/powerpc/cpu/mpc8xxx/ddr/options.c
@@ -13,28 +13,338 @@
#include "ddr.h"
+/*
+ * Use our own stack based buffer before relocation to allow accessing longer
+ * hwconfig strings that might be in the environment before we've relocated.
+ * This is pretty fragile on both the use of stack and if the buffer is big
+ * enough. However we will get a warning from getenv_f for the later.
+ */
+#define HWCONFIG_BUFFER_SIZE 128
+
/* Board-specific functions defined in each board's ddr.c */
extern void fsl_ddr_board_options(memctl_options_t *popts,
dimm_params_t *pdimm,
unsigned int ctrl_num);
+typedef struct {
+ unsigned int odt_rd_cfg;
+ unsigned int odt_wr_cfg;
+ unsigned int odt_rtt_norm;
+ unsigned int odt_rtt_wr;
+} dynamic_odt_t;
+
+static const dynamic_odt_t single_Q[4] = {
+ { /* cs0 */
+ FSL_DDR_ODT_NEVER,
+ FSL_DDR_ODT_CS_AND_OTHER_DIMM,
+ DDR3_RTT_20_OHM,
+ DDR3_RTT_120_OHM
+ },
+ { /* cs1 */
+ FSL_DDR_ODT_NEVER,
+ FSL_DDR_ODT_NEVER, /* tied high */
+ DDR3_RTT_OFF,
+ DDR3_RTT_120_OHM
+ },
+ { /* cs2 */
+ FSL_DDR_ODT_NEVER,
+ FSL_DDR_ODT_CS_AND_OTHER_DIMM,
+ DDR3_RTT_20_OHM,
+ DDR3_RTT_120_OHM
+ },
+ { /* cs3 */
+ FSL_DDR_ODT_NEVER,
+ FSL_DDR_ODT_NEVER, /* tied high */
+ DDR3_RTT_OFF,
+ DDR3_RTT_120_OHM
+ }
+};
+
+static const dynamic_odt_t single_D[4] = {
+ { /* cs0 */
+ FSL_DDR_ODT_NEVER,
+ FSL_DDR_ODT_ALL,
+ DDR3_RTT_40_OHM,
+ DDR3_RTT_OFF
+ },
+ { /* cs1 */
+ FSL_DDR_ODT_NEVER,
+ FSL_DDR_ODT_NEVER,
+ DDR3_RTT_OFF,
+ DDR3_RTT_OFF
+ },
+ {0, 0, 0, 0},
+ {0, 0, 0, 0}
+};
+
+static const dynamic_odt_t single_S[4] = {
+ { /* cs0 */
+ FSL_DDR_ODT_NEVER,
+ FSL_DDR_ODT_ALL,
+ DDR3_RTT_40_OHM,
+ DDR3_RTT_OFF
+ },
+ {0, 0, 0, 0},
+ {0, 0, 0, 0},
+ {0, 0, 0, 0},
+};
+
+static const dynamic_odt_t dual_DD[4] = {
+ { /* cs0 */
+ FSL_DDR_ODT_NEVER,
+ FSL_DDR_ODT_SAME_DIMM,
+ DDR3_RTT_120_OHM,
+ DDR3_RTT_OFF
+ },
+ { /* cs1 */
+ FSL_DDR_ODT_OTHER_DIMM,
+ FSL_DDR_ODT_OTHER_DIMM,
+ DDR3_RTT_30_OHM,
+ DDR3_RTT_OFF
+ },
+ { /* cs2 */
+ FSL_DDR_ODT_NEVER,
+ FSL_DDR_ODT_SAME_DIMM,
+ DDR3_RTT_120_OHM,
+ DDR3_RTT_OFF
+ },
+ { /* cs3 */
+ FSL_DDR_ODT_OTHER_DIMM,
+ FSL_DDR_ODT_OTHER_DIMM,
+ DDR3_RTT_30_OHM,
+ DDR3_RTT_OFF
+ }
+};
+
+static const dynamic_odt_t dual_DS[4] = {
+ { /* cs0 */
+ FSL_DDR_ODT_NEVER,
+ FSL_DDR_ODT_SAME_DIMM,
+ DDR3_RTT_120_OHM,
+ DDR3_RTT_OFF
+ },
+ { /* cs1 */
+ FSL_DDR_ODT_OTHER_DIMM,
+ FSL_DDR_ODT_OTHER_DIMM,
+ DDR3_RTT_30_OHM,
+ DDR3_RTT_OFF
+ },
+ { /* cs2 */
+ FSL_DDR_ODT_OTHER_DIMM,
+ FSL_DDR_ODT_ALL,
+ DDR3_RTT_20_OHM,
+ DDR3_RTT_120_OHM
+ },
+ {0, 0, 0, 0}
+};
+static const dynamic_odt_t dual_SD[4] = {
+ { /* cs0 */
+ FSL_DDR_ODT_OTHER_DIMM,
+ FSL_DDR_ODT_ALL,
+ DDR3_RTT_20_OHM,
+ DDR3_RTT_120_OHM
+ },
+ {0, 0, 0, 0},
+ { /* cs2 */
+ FSL_DDR_ODT_NEVER,
+ FSL_DDR_ODT_SAME_DIMM,
+ DDR3_RTT_120_OHM,
+ DDR3_RTT_OFF
+ },
+ { /* cs3 */
+ FSL_DDR_ODT_OTHER_DIMM,
+ FSL_DDR_ODT_OTHER_DIMM,
+ DDR3_RTT_20_OHM,
+ DDR3_RTT_OFF
+ }
+};
+
+static const dynamic_odt_t dual_SS[4] = {
+ { /* cs0 */
+ FSL_DDR_ODT_OTHER_DIMM,
+ FSL_DDR_ODT_ALL,
+ DDR3_RTT_30_OHM,
+ DDR3_RTT_120_OHM
+ },
+ {0, 0, 0, 0},
+ { /* cs2 */
+ FSL_DDR_ODT_OTHER_DIMM,
+ FSL_DDR_ODT_ALL,
+ DDR3_RTT_30_OHM,
+ DDR3_RTT_120_OHM
+ },
+ {0, 0, 0, 0}
+};
+
+static const dynamic_odt_t dual_D0[4] = {
+ { /* cs0 */
+ FSL_DDR_ODT_NEVER,
+ FSL_DDR_ODT_SAME_DIMM,
+ DDR3_RTT_40_OHM,
+ DDR3_RTT_OFF
+ },
+ { /* cs1 */
+ FSL_DDR_ODT_NEVER,
+ FSL_DDR_ODT_NEVER,
+ DDR3_RTT_OFF,
+ DDR3_RTT_OFF
+ },
+ {0, 0, 0, 0},
+ {0, 0, 0, 0}
+};
+
+static const dynamic_odt_t dual_0D[4] = {
+ {0, 0, 0, 0},
+ {0, 0, 0, 0},
+ { /* cs2 */
+ FSL_DDR_ODT_NEVER,
+ FSL_DDR_ODT_SAME_DIMM,
+ DDR3_RTT_40_OHM,
+ DDR3_RTT_OFF
+ },
+ { /* cs3 */
+ FSL_DDR_ODT_NEVER,
+ FSL_DDR_ODT_NEVER,
+ DDR3_RTT_OFF,
+ DDR3_RTT_OFF
+ }
+};
+
+static const dynamic_odt_t dual_S0[4] = {
+ { /* cs0 */
+ FSL_DDR_ODT_NEVER,
+ FSL_DDR_ODT_CS,
+ DDR3_RTT_40_OHM,
+ DDR3_RTT_OFF
+ },
+ {0, 0, 0, 0},
+ {0, 0, 0, 0},
+ {0, 0, 0, 0}
+
+};
+
+static const dynamic_odt_t dual_0S[4] = {
+ {0, 0, 0, 0},
+ {0, 0, 0, 0},
+ { /* cs2 */
+ FSL_DDR_ODT_NEVER,
+ FSL_DDR_ODT_CS,
+ DDR3_RTT_40_OHM,
+ DDR3_RTT_OFF
+ },
+ {0, 0, 0, 0}
+
+};
+
+static const dynamic_odt_t odt_unknown[4] = {
+ { /* cs0 */
+ FSL_DDR_ODT_NEVER,
+ FSL_DDR_ODT_CS,
+ DDR3_RTT_120_OHM,
+ DDR3_RTT_OFF
+ },
+ { /* cs1 */
+ FSL_DDR_ODT_NEVER,
+ FSL_DDR_ODT_CS,
+ DDR3_RTT_120_OHM,
+ DDR3_RTT_OFF
+ },
+ { /* cs2 */
+ FSL_DDR_ODT_NEVER,
+ FSL_DDR_ODT_CS,
+ DDR3_RTT_120_OHM,
+ DDR3_RTT_OFF
+ },
+ { /* cs3 */
+ FSL_DDR_ODT_NEVER,
+ FSL_DDR_ODT_CS,
+ DDR3_RTT_120_OHM,
+ DDR3_RTT_OFF
+ }
+};
+
unsigned int populate_memctl_options(int all_DIMMs_registered,
memctl_options_t *popts,
dimm_params_t *pdimm,
unsigned int ctrl_num)
{
unsigned int i;
+ char buffer[HWCONFIG_BUFFER_SIZE];
+ char *buf = NULL;
+ const dynamic_odt_t *pdodt = odt_unknown;
+
+ /*
+ * Extract hwconfig from environment since we have not properly setup
+ * the environment but need it for ddr config params
+ */
+ if (getenv_f("hwconfig", buffer, sizeof(buffer)) > 0)
+ buf = buffer;
/* Chip select options. */
+ if (CONFIG_DIMM_SLOTS_PER_CTLR == 1) {
+ switch (pdimm[0].n_ranks) {
+ case 1:
+ pdodt = single_S;
+ break;
+ case 2:
+ pdodt = single_D;
+ break;
+ case 4:
+ pdodt = single_Q;
+ break;
+ }
+ } else if (CONFIG_DIMM_SLOTS_PER_CTLR == 2) {
+ switch (pdimm[0].n_ranks) {
+ case 2:
+ switch (pdimm[1].n_ranks) {
+ case 2:
+ pdodt = dual_DD;
+ break;
+ case 1:
+ pdodt = dual_DS;
+ break;
+ case 0:
+ pdodt = dual_D0;
+ break;
+ }
+ break;
+ case 1:
+ switch (pdimm[1].n_ranks) {
+ case 2:
+ pdodt = dual_SD;
+ break;
+ case 1:
+ pdodt = dual_SS;
+ break;
+ case 0:
+ pdodt = dual_S0;
+ break;
+ }
+ break;
+ case 0:
+ switch (pdimm[1].n_ranks) {
+ case 2:
+ pdodt = dual_0D;
+ break;
+ case 1:
+ pdodt = dual_0S;
+ break;
+ }
+ break;
+ }
+ }
/* Pick chip-select local options. */
for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
- /* If not DDR2, odt_rd_cfg and odt_wr_cfg need to be 0. */
-
- /* only for single CS? */
- popts->cs_local_opts[i].odt_rd_cfg = 0;
-
- popts->cs_local_opts[i].odt_wr_cfg = 1;
+#if defined(CONFIG_FSL_DDR3)
+ popts->cs_local_opts[i].odt_rd_cfg = pdodt[i].odt_rd_cfg;
+ popts->cs_local_opts[i].odt_wr_cfg = pdodt[i].odt_wr_cfg;
+ popts->cs_local_opts[i].odt_rtt_norm = pdodt[i].odt_rtt_norm;
+ popts->cs_local_opts[i].odt_rtt_wr = pdodt[i].odt_rtt_wr;
+#else
+ popts->cs_local_opts[i].odt_rd_cfg = FSL_DDR_ODT_NEVER;
+ popts->cs_local_opts[i].odt_wr_cfg = FSL_DDR_ODT_CS;
+#endif
popts->cs_local_opts[i].auto_precharge = 0;
}
@@ -81,10 +391,13 @@ unsigned int populate_memctl_options(int all_DIMMs_registered,
/* Operational Mode Paramters */
/* Pick ECC modes */
-#ifdef CONFIG_DDR_ECC
- popts->ECC_mode = 1; /* 0 = disabled, 1 = enabled */
-#else
popts->ECC_mode = 0; /* 0 = disabled, 1 = enabled */
+#ifdef CONFIG_DDR_ECC
+ if (hwconfig_sub_f("fsl_ddr", "ecc", buf)) {
+ if (hwconfig_subarg_cmp_f("fsl_ddr", "ecc", "on", buf))
+ popts->ECC_mode = 1;
+ } else
+ popts->ECC_mode = 1;
#endif
popts->ECC_init_using_memctl = 1; /* 0 = use DMA, 1 = use memctl */
@@ -159,6 +472,9 @@ unsigned int populate_memctl_options(int all_DIMMs_registered,
popts->twoT_en = 0;
popts->threeT_en = 0;
+ /* for RDIMM, address parity enable */
+ popts->ap_en = 1;
+
/*
* BSTTOPRE precharge interval
*
@@ -221,7 +537,7 @@ unsigned int populate_memctl_options(int all_DIMMs_registered,
* should be a subset of the requested configuration.
*/
#if (CONFIG_NUM_DDR_CONTROLLERS > 1)
- if (hwconfig_sub("fsl_ddr", "ctlr_intlv")) {
+ if (hwconfig_sub_f("fsl_ddr", "ctlr_intlv", buf)) {
if (pdimm[0].n_ranks == 0) {
printf("There is no rank on CS0 for controller %d. Because only"
" rank on CS0 and ranks chip-select interleaved with CS0"
@@ -234,19 +550,25 @@ unsigned int populate_memctl_options(int all_DIMMs_registered,
* test null first. if CONFIG_HWCONFIG is not defined
* hwconfig_arg_cmp returns non-zero
*/
- if (hwconfig_subarg_cmp("fsl_ddr", "ctlr_intlv", "null")) {
+ if (hwconfig_subarg_cmp_f("fsl_ddr", "ctlr_intlv",
+ "null", buf)) {
popts->memctl_interleaving = 0;
debug("memory controller interleaving disabled.\n");
- } else if (hwconfig_subarg_cmp("fsl_ddr", "ctlr_intlv", "cacheline"))
+ } else if (hwconfig_subarg_cmp_f("fsl_ddr",
+ "ctlr_intlv",
+ "cacheline", buf))
popts->memctl_interleaving_mode =
FSL_DDR_CACHE_LINE_INTERLEAVING;
- else if (hwconfig_subarg_cmp("fsl_ddr", "ctlr_intlv", "page"))
+ else if (hwconfig_subarg_cmp_f("fsl_ddr", "ctlr_intlv",
+ "page", buf))
popts->memctl_interleaving_mode =
FSL_DDR_PAGE_INTERLEAVING;
- else if (hwconfig_subarg_cmp("fsl_ddr", "ctlr_intlv", "bank"))
+ else if (hwconfig_subarg_cmp_f("fsl_ddr", "ctlr_intlv",
+ "bank", buf))
popts->memctl_interleaving_mode =
FSL_DDR_BANK_INTERLEAVING;
- else if (hwconfig_subarg_cmp("fsl_ddr", "ctlr_intlv", "superbank"))
+ else if (hwconfig_subarg_cmp_f("fsl_ddr", "ctlr_intlv",
+ "superbank", buf))
popts->memctl_interleaving_mode =
FSL_DDR_SUPERBANK_INTERLEAVING;
else {
@@ -256,19 +578,24 @@ unsigned int populate_memctl_options(int all_DIMMs_registered,
}
}
#endif
- if ((hwconfig_sub("fsl_ddr", "bank_intlv")) &&
+ if ((hwconfig_sub_f("fsl_ddr", "bank_intlv", buf)) &&
(CONFIG_CHIP_SELECTS_PER_CTRL > 1)) {
/* test null first. if CONFIG_HWCONFIG is not defined,
- * hwconfig_arg_cmp returns non-zero */
- if (hwconfig_subarg_cmp("fsl_ddr", "bank_intlv", "null"))
+ * hwconfig_subarg_cmp_f returns non-zero */
+ if (hwconfig_subarg_cmp_f("fsl_ddr", "bank_intlv",
+ "null", buf))
debug("bank interleaving disabled.\n");
- else if (hwconfig_subarg_cmp("fsl_ddr", "bank_intlv", "cs0_cs1"))
+ else if (hwconfig_subarg_cmp_f("fsl_ddr", "bank_intlv",
+ "cs0_cs1", buf))
popts->ba_intlv_ctl = FSL_DDR_CS0_CS1;
- else if (hwconfig_subarg_cmp("fsl_ddr", "bank_intlv", "cs2_cs3"))
+ else if (hwconfig_subarg_cmp_f("fsl_ddr", "bank_intlv",
+ "cs2_cs3", buf))
popts->ba_intlv_ctl = FSL_DDR_CS2_CS3;
- else if (hwconfig_subarg_cmp("fsl_ddr", "bank_intlv", "cs0_cs1_and_cs2_cs3"))
+ else if (hwconfig_subarg_cmp_f("fsl_ddr", "bank_intlv",
+ "cs0_cs1_and_cs2_cs3", buf))
popts->ba_intlv_ctl = FSL_DDR_CS0_CS1_AND_CS2_CS3;
- else if (hwconfig_subarg_cmp("fsl_ddr", "bank_intlv", "cs0_cs1_cs2_cs3"))
+ else if (hwconfig_subarg_cmp_f("fsl_ddr", "bank_intlv",
+ "cs0_cs1_cs2_cs3", buf))
popts->ba_intlv_ctl = FSL_DDR_CS0_CS1_CS2_CS3;
else
printf("hwconfig has unrecognized parameter for bank_intlv.\n");
@@ -342,10 +669,11 @@ unsigned int populate_memctl_options(int all_DIMMs_registered,
}
}
- if (hwconfig_sub("fsl_ddr", "addr_hash")) {
- if (hwconfig_subarg_cmp("fsl_ddr", "addr_hash", "null"))
+ if (hwconfig_sub_f("fsl_ddr", "addr_hash", buf)) {
+ if (hwconfig_subarg_cmp_f("fsl_ddr", "addr_hash", "null", buf))
popts->addr_hash = 0;
- else if (hwconfig_subarg_cmp("fsl_ddr", "addr_hash", "true"))
+ else if (hwconfig_subarg_cmp_f("fsl_ddr", "addr_hash",
+ "true", buf))
popts->addr_hash = 1;
}
@@ -393,11 +721,22 @@ int fsl_use_spd(void)
int use_spd = 0;
#ifdef CONFIG_DDR_SPD
+ char buffer[HWCONFIG_BUFFER_SIZE];
+ char *buf = NULL;
+
+ /*
+ * Extract hwconfig from environment since we have not properly setup
+ * the environment but need it for ddr config params
+ */
+ if (getenv_f("hwconfig", buffer, sizeof(buffer)) > 0)
+ buf = buffer;
+
/* if hwconfig is not enabled, or "sdram" is not defined, use spd */
- if (hwconfig_sub("fsl_ddr", "sdram")) {
- if (hwconfig_subarg_cmp("fsl_ddr", "sdram", "spd"))
+ if (hwconfig_sub_f("fsl_ddr", "sdram", buf)) {
+ if (hwconfig_subarg_cmp_f("fsl_ddr", "sdram", "spd", buf))
use_spd = 1;
- else if (hwconfig_subarg_cmp("fsl_ddr", "sdram", "fixed"))
+ else if (hwconfig_subarg_cmp_f("fsl_ddr", "sdram",
+ "fixed", buf))
use_spd = 0;
else
use_spd = 1;
diff --git a/arch/powerpc/include/asm/config.h b/arch/powerpc/include/asm/config.h
index 76dedeb..2b6b233 100644
--- a/arch/powerpc/include/asm/config.h
+++ b/arch/powerpc/include/asm/config.h
@@ -1,5 +1,5 @@
/*
- * Copyright 2009-2010 Freescale Semiconductor, Inc.
+ * Copyright 2009-2011 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
@@ -21,6 +21,14 @@
#ifndef _ASM_CONFIG_H_
#define _ASM_CONFIG_H_
+#ifdef CONFIG_MPC85xx
+#include <asm/config_mpc85xx.h>
+#endif
+
+#ifdef CONFIG_MPC86xx
+#include <asm/config_mpc86xx.h>
+#endif
+
#define CONFIG_LMB
#define CONFIG_SYS_BOOT_RAMDISK_HIGH
#define CONFIG_SYS_BOOT_GET_CMDLINE
@@ -43,17 +51,7 @@
#endif
#endif
-#if defined(CONFIG_MPC8572) || defined(CONFIG_P1020) || \
- defined(CONFIG_P1021) || defined(CONFIG_P1022) || \
- defined(CONFIG_P2020) || defined(CONFIG_MPC8641)
-#define CONFIG_MAX_CPUS 2
-#elif defined(CONFIG_PPC_P3041)
-#define CONFIG_MAX_CPUS 4
-#elif defined(CONFIG_PPC_P4080)
-#define CONFIG_MAX_CPUS 8
-#elif defined(CONFIG_PPC_P5020)
-#define CONFIG_MAX_CPUS 2
-#else
+#ifndef CONFIG_MAX_CPUS
#define CONFIG_MAX_CPUS 1
#endif
@@ -67,28 +65,13 @@
#endif
#endif
-/* Enable TSEC2.0 for the platforms that have it if we are using TSEC */
-#if defined(CONFIG_TSEC_ENET) && \
- (defined(CONFIG_P1020) || defined(CONFIG_P1011))
-#define CONFIG_TSECV2
-#endif
-
/*
* SEC (crypto unit) major compatible version determination
*/
-#if defined(CONFIG_FSL_CORENET)
-#define CONFIG_SYS_FSL_SEC_COMPAT 4
-#elif defined(CONFIG_MPC85xx) || defined(CONFIG_MPC83xx)
+#if defined(CONFIG_MPC83xx)
#define CONFIG_SYS_FSL_SEC_COMPAT 2
#endif
-/* Number of TLB CAM entries we have on FSL Book-E chips */
-#if defined(CONFIG_E500MC)
-#define CONFIG_SYS_NUM_TLBCAMS 64
-#elif defined(CONFIG_E500)
-#define CONFIG_SYS_NUM_TLBCAMS 16
-#endif
-
/* Since so many PPC SOCs have a semi-common LBC, define this here */
#if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx) || \
defined(CONFIG_MPC83xx)
diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h
new file mode 100644
index 0000000..5792f2f
--- /dev/null
+++ b/arch/powerpc/include/asm/config_mpc85xx.h
@@ -0,0 +1,188 @@
+/*
+ * Copyright 2011 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#ifndef _ASM_MPC85xx_CONFIG_H_
+#define _ASM_MPC85xx_CONFIG_H_
+
+/* SoC specific defines for Freescale MPC85xx (PQ3) and QorIQ processors */
+
+/* Number of TLB CAM entries we have on FSL Book-E chips */
+#if defined(CONFIG_E500MC)
+#define CONFIG_SYS_NUM_TLBCAMS 64
+#elif defined(CONFIG_E500)
+#define CONFIG_SYS_NUM_TLBCAMS 16
+#endif
+
+#if defined(CONFIG_MPC8536)
+#define CONFIG_MAX_CPUS 1
+#define CONFIG_SYS_FSL_NUM_LAWS 12
+#define CONFIG_SYS_FSL_SEC_COMPAT 2
+
+#elif defined(CONFIG_MPC8540)
+#define CONFIG_MAX_CPUS 1
+#define CONFIG_SYS_FSL_NUM_LAWS 8
+
+#elif defined(CONFIG_MPC8541)
+#define CONFIG_MAX_CPUS 1
+#define CONFIG_SYS_FSL_NUM_LAWS 8
+#define CONFIG_SYS_FSL_SEC_COMPAT 2
+
+#elif defined(CONFIG_MPC8544)
+#define CONFIG_MAX_CPUS 1
+#define CONFIG_SYS_FSL_NUM_LAWS 10
+#define CONFIG_SYS_FSL_SEC_COMPAT 2
+
+#elif defined(CONFIG_MPC8548)
+#define CONFIG_MAX_CPUS 1
+#define CONFIG_SYS_FSL_NUM_LAWS 10
+#define CONFIG_SYS_FSL_SEC_COMPAT 2
+
+#elif defined(CONFIG_MPC8555)
+#define CONFIG_MAX_CPUS 1
+#define CONFIG_SYS_FSL_NUM_LAWS 8
+#define CONFIG_SYS_FSL_SEC_COMPAT 2
+
+#elif defined(CONFIG_MPC8560)
+#define CONFIG_MAX_CPUS 1
+#define CONFIG_SYS_FSL_NUM_LAWS 8
+
+#elif defined(CONFIG_MPC8568)
+#define CONFIG_MAX_CPUS 1
+#define CONFIG_SYS_FSL_NUM_LAWS 10
+#define CONFIG_SYS_FSL_SEC_COMPAT 2
+
+#elif defined(CONFIG_MPC8569)
+#define CONFIG_MAX_CPUS 1
+#define CONFIG_SYS_FSL_NUM_LAWS 10
+#define CONFIG_SYS_FSL_SEC_COMPAT 2
+
+#elif defined(CONFIG_MPC8572)
+#define CONFIG_MAX_CPUS 2
+#define CONFIG_SYS_FSL_NUM_LAWS 12
+#define CONFIG_SYS_FSL_SEC_COMPAT 2
+
+#elif defined(CONFIG_P1010)
+#define CONFIG_MAX_CPUS 1
+#define CONFIG_SYS_FSL_NUM_LAWS 12
+#define CONFIG_TSECV2
+#define CONFIG_SYS_FSL_SEC_COMPAT 4
+
+#elif defined(CONFIG_P1011)
+#define CONFIG_MAX_CPUS 1
+#define CONFIG_SYS_FSL_NUM_LAWS 12
+#define CONFIG_TSECV2
+#define CONFIG_SYS_FSL_SEC_COMPAT 2
+
+#elif defined(CONFIG_P1012)
+#define CONFIG_MAX_CPUS 1
+#define CONFIG_SYS_FSL_NUM_LAWS 12
+#define CONFIG_TSECV2
+#define CONFIG_SYS_FSL_SEC_COMPAT 2
+
+#elif defined(CONFIG_P1013)
+#define CONFIG_MAX_CPUS 1
+#define CONFIG_SYS_FSL_NUM_LAWS 12
+#define CONFIG_TSECV2
+#define CONFIG_SYS_FSL_SEC_COMPAT 2
+
+#elif defined(CONFIG_P1014)
+#define CONFIG_MAX_CPUS 1
+#define CONFIG_SYS_FSL_NUM_LAWS 12
+#define CONFIG_TSECV2
+#define CONFIG_SYS_FSL_SEC_COMPAT 4
+
+#elif defined(CONFIG_P1020)
+#define CONFIG_MAX_CPUS 2
+#define CONFIG_SYS_FSL_NUM_LAWS 12
+#define CONFIG_TSECV2
+#define CONFIG_SYS_FSL_SEC_COMPAT 2
+
+#elif defined(CONFIG_P1021)
+#define CONFIG_MAX_CPUS 2
+#define CONFIG_SYS_FSL_NUM_LAWS 12
+#define CONFIG_TSECV2
+#define CONFIG_SYS_FSL_SEC_COMPAT 2
+
+#elif defined(CONFIG_P1022)
+#define CONFIG_MAX_CPUS 2
+#define CONFIG_SYS_FSL_NUM_LAWS 12
+#define CONFIG_TSECV2
+#define CONFIG_SYS_FSL_SEC_COMPAT 2
+
+#elif defined(CONFIG_P2010)
+#define CONFIG_MAX_CPUS 1
+#define CONFIG_SYS_FSL_NUM_LAWS 12
+#define CONFIG_SYS_FSL_SEC_COMPAT 2
+
+#elif defined(CONFIG_P2020)
+#define CONFIG_MAX_CPUS 2
+#define CONFIG_SYS_FSL_NUM_LAWS 12
+#define CONFIG_SYS_FSL_SEC_COMPAT 2
+
+#elif defined(CONFIG_PPC_P2040)
+#define CONFIG_MAX_CPUS 4
+#define CONFIG_SYS_FSL_NUM_LAWS 32
+#define CONFIG_SYS_FSL_SEC_COMPAT 4
+
+#elif defined(CONFIG_PPC_P3041)
+#define CONFIG_MAX_CPUS 4
+#define CONFIG_SYS_FSL_NUM_LAWS 32
+#define CONFIG_SYS_FSL_SEC_COMPAT 4
+
+#elif defined(CONFIG_PPC_P4040)
+#define CONFIG_MAX_CPUS 4
+#define CONFIG_SYS_FSL_NUM_LAWS 32
+#define CONFIG_SYS_FSL_SEC_COMPAT 4
+
+#elif defined(CONFIG_PPC_P4080)
+#define CONFIG_MAX_CPUS 8
+#define CONFIG_SYS_FSL_NUM_LAWS 32
+#define CONFIG_SYS_FSL_SEC_COMPAT 4
+#define CONFIG_SYS_NUM_FMAN 2
+#define CONFIG_SYS_NUM_FM1_DTSEC 4
+#define CONFIG_SYS_NUM_FM2_DTSEC 4
+#define CONFIG_SYS_NUM_FM1_10GEC 1
+#define CONFIG_SYS_NUM_FM2_10GEC 1
+#define CONFIG_NUM_DDR_CONTROLLERS 2
+#define CONFIG_SYS_FSL_ERRATUM_CPC_A002
+#define CONFIG_SYS_FSL_ERRATUM_CPC_A003
+#define CONFIG_SYS_FSL_ERRATUM_DDR_A003
+#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
+#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
+#define CONFIG_SYS_FSL_ERRATUM_ESDHC135
+#define CONFIG_SYS_FSL_ERRATUM_ESDHC136
+#define CONFIG_SYS_P4080_ERRATUM_CPU22
+#define CONFIG_SYS_P4080_ERRATUM_SERDES8
+
+#elif defined(CONFIG_PPC_P5010)
+#define CONFIG_MAX_CPUS 1
+#define CONFIG_SYS_FSL_NUM_LAWS 32
+#define CONFIG_SYS_FSL_SEC_COMPAT 4
+
+#elif defined(CONFIG_PPC_P5020)
+#define CONFIG_MAX_CPUS 2
+#define CONFIG_SYS_FSL_NUM_LAWS 32
+#define CONFIG_SYS_FSL_SEC_COMPAT 4
+
+#else
+#error Processor type not defined for this platform
+#endif
+
+#endif /* _ASM_MPC85xx_CONFIG_H_ */
diff --git a/arch/powerpc/include/asm/config_mpc86xx.h b/arch/powerpc/include/asm/config_mpc86xx.h
new file mode 100644
index 0000000..c5c1ef4
--- /dev/null
+++ b/arch/powerpc/include/asm/config_mpc86xx.h
@@ -0,0 +1,38 @@
+/*
+ * Copyright 2011 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#ifndef _ASM_MPC86xx_CONFIG_H_
+#define _ASM_MPC86xx_CONFIG_H_
+
+/* SoC specific defines for Freescale MPC86xx processors */
+
+#if defined(CONFIG_MPC8610)
+#define CONFIG_MAX_CPUS 1
+#define CONFIG_SYS_FSL_NUM_LAWS 10
+
+#elif defined(CONFIG_MPC8641)
+#define CONFIG_MAX_CPUS 2
+#define CONFIG_SYS_FSL_NUM_LAWS 10
+
+#else
+#error Processor type not defined for this platform
+#endif
+
+#endif /* _ASM_MPC85xx_CONFIG_H_ */
diff --git a/arch/powerpc/include/asm/fsl_ddr_sdram.h b/arch/powerpc/include/asm/fsl_ddr_sdram.h
index 3de2113..852e5c3 100644
--- a/arch/powerpc/include/asm/fsl_ddr_sdram.h
+++ b/arch/powerpc/include/asm/fsl_ddr_sdram.h
@@ -24,6 +24,7 @@
#define DDR_OTF 6 /* on-the-fly BC4 and BL8 */
#define DDR_BL8 8 /* burst length 8 */
+#define DDR3_RTT_OFF 0
#define DDR3_RTT_60_OHM 1 /* RTT_Nom = RZQ/4 */
#define DDR3_RTT_120_OHM 2 /* RTT_Nom = RZQ/2 */
#define DDR3_RTT_40_OHM 3 /* RTT_Nom = RZQ/6 */
@@ -50,6 +51,15 @@ typedef ddr3_spd_eeprom_t generic_spd_eeprom_t;
#endif
#endif /* #if defined(CONFIG_FSL_DDR1) */
+#define FSL_DDR_ODT_NEVER 0x0
+#define FSL_DDR_ODT_CS 0x1
+#define FSL_DDR_ODT_ALL_OTHER_CS 0x2
+#define FSL_DDR_ODT_OTHER_DIMM 0x3
+#define FSL_DDR_ODT_ALL 0x4
+#define FSL_DDR_ODT_SAME_DIMM 0x5
+#define FSL_DDR_ODT_CS_AND_OTHER_DIMM 0x6
+#define FSL_DDR_ODT_OTHER_CS_ONSAMEDIMM 0x7
+
/* define bank(chip select) interleaving mode */
#define FSL_DDR_CS0_CS1 0x40
#define FSL_DDR_CS2_CS3 0x20
@@ -91,6 +101,28 @@ typedef ddr3_spd_eeprom_t generic_spd_eeprom_t;
#define WR_DATA_DELAY_SHIFT 10
#endif
+/* DDR_MD_CNTL */
+#define MD_CNTL_MD_EN 0x80000000
+#define MD_CNTL_CS_SEL_CS0 0x00000000
+#define MD_CNTL_CS_SEL_CS1 0x10000000
+#define MD_CNTL_CS_SEL_CS2 0x20000000
+#define MD_CNTL_CS_SEL_CS3 0x30000000
+#define MD_CNTL_CS_SEL_CS0_CS1 0x40000000
+#define MD_CNTL_CS_SEL_CS2_CS3 0x50000000
+#define MD_CNTL_MD_SEL_MR 0x00000000
+#define MD_CNTL_MD_SEL_EMR 0x01000000
+#define MD_CNTL_MD_SEL_EMR2 0x02000000
+#define MD_CNTL_MD_SEL_EMR3 0x03000000
+#define MD_CNTL_SET_REF 0x00800000
+#define MD_CNTL_SET_PRE 0x00400000
+#define MD_CNTL_CKE_CNTL_LOW 0x00100000
+#define MD_CNTL_CKE_CNTL_HIGH 0x00200000
+#define MD_CNTL_WRCW 0x00080000
+#define MD_CNTL_MD_VALUE(x) (x & 0x0000FFFF)
+
+/* DDR_CDR1 */
+#define DDR_CDR1_DHC_EN 0x80000000
+
/* Record of register values computed */
typedef struct fsl_ddr_cfg_regs_s {
struct {
@@ -106,6 +138,12 @@ typedef struct fsl_ddr_cfg_regs_s {
unsigned int ddr_sdram_cfg_2;
unsigned int ddr_sdram_mode;
unsigned int ddr_sdram_mode_2;
+ unsigned int ddr_sdram_mode_3;
+ unsigned int ddr_sdram_mode_4;
+ unsigned int ddr_sdram_mode_5;
+ unsigned int ddr_sdram_mode_6;
+ unsigned int ddr_sdram_mode_7;
+ unsigned int ddr_sdram_mode_8;
unsigned int ddr_sdram_md_cntl;
unsigned int ddr_sdram_interval;
unsigned int ddr_data_init;
@@ -120,6 +158,11 @@ typedef struct fsl_ddr_cfg_regs_s {
unsigned int ddr_sdram_rcw_1;
unsigned int ddr_sdram_rcw_2;
unsigned int ddr_eor;
+ unsigned int ddr_cdr1;
+ unsigned int ddr_cdr2;
+ unsigned int err_disable;
+ unsigned int err_int_en;
+ unsigned int debug[32];
} fsl_ddr_cfg_regs_t;
typedef struct memctl_options_partial_s {
@@ -151,6 +194,8 @@ typedef struct memctl_options_s {
unsigned int auto_precharge;
unsigned int odt_rd_cfg;
unsigned int odt_wr_cfg;
+ unsigned int odt_rtt_norm;
+ unsigned int odt_rtt_wr;
} cs_local_opts[CONFIG_CHIP_SELECTS_PER_CTRL];
/* Special configurations for chip select */
@@ -175,6 +220,7 @@ typedef struct memctl_options_s {
/* mirrior DIMMs for DDR3 */
unsigned int mirrored_dimm;
unsigned int quad_rank_present;
+ unsigned int ap_en; /* address parity enable for RDIMM */
/* Global Timing Parameters */
unsigned int cas_latency_override;
@@ -210,6 +256,12 @@ typedef struct memctl_options_s {
unsigned int zq_en;
/* Write leveling */
unsigned int wrlvl_en;
+ /* RCW override for RDIMM */
+ unsigned int rcw_override;
+ unsigned int rcw_1;
+ unsigned int rcw_2;
+ /* control register 1 */
+ unsigned int ddr_cdr1;
} memctl_options_t;
extern phys_size_t fsl_ddr_sdram(void);
diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h
index b96dec7..6bd83ba 100644
--- a/arch/powerpc/include/asm/immap_85xx.h
+++ b/arch/powerpc/include/asm/immap_85xx.h
@@ -222,25 +222,8 @@ typedef struct ccsr_ddr {
u32 capture_ext_address; /* Error Extended Addr Capture */
u32 err_sbe; /* Single-Bit ECC Error Management */
u8 res11[164];
- u32 debug_1;
- u32 debug_2;
- u32 debug_3;
- u32 debug_4;
- u32 debug_5;
- u32 debug_6;
- u32 debug_7;
- u32 debug_8;
- u32 debug_9;
- u32 debug_10;
- u32 debug_11;
- u32 debug_12;
- u32 debug_13;
- u32 debug_14;
- u32 debug_15;
- u32 debug_16;
- u32 debug_17;
- u32 debug_18;
- u8 res12[184];
+ u32 debug[32]; /* debug_1 to debug_32 */
+ u8 res12[128];
} ccsr_ddr_t;
#define DDR_EOR_RD_BDW_OPT_DIS 0x80000000 /* Read BDW Opt. disable */
@@ -2309,7 +2292,7 @@ typedef struct ccsr_pme {
#define CONFIG_SYS_MPC85xx_CPM_ADDR \
(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_CPM_OFFSET)
#define CONFIG_SYS_MPC85xx_SERDES1_ADDR \
- (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SERDES2_OFFSET)
+ (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SERDES1_OFFSET)
#define CONFIG_SYS_MPC85xx_SERDES2_ADDR \
(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SERDES2_OFFSET)
#define CONFIG_SYS_FSL_CORENET_SERDES_ADDR \
diff --git a/arch/powerpc/include/asm/processor.h b/arch/powerpc/include/asm/processor.h
index 71fafa3..fcee1a2 100644
--- a/arch/powerpc/include/asm/processor.h
+++ b/arch/powerpc/include/asm/processor.h
@@ -1038,12 +1038,16 @@
#define SVR_8569_E 0x808800
#define SVR_8572 0x80E000
#define SVR_8572_E 0x80E800
+#define SVR_P1010 0x80F100
+#define SVR_P1010_E 0x80F900
#define SVR_P1011 0x80E500
#define SVR_P1011_E 0x80ED00
#define SVR_P1012 0x80E501
#define SVR_P1012_E 0x80ED01
#define SVR_P1013 0x80E700
#define SVR_P1013_E 0x80EF00
+#define SVR_P1014 0x80F101
+#define SVR_P1014_E 0x80F901
#define SVR_P1020 0x80E400
#define SVR_P1020_E 0x80EC00
#define SVR_P1021 0x80E401
@@ -1054,6 +1058,8 @@
#define SVR_P2010_E 0x80EB00
#define SVR_P2020 0x80E200
#define SVR_P2020_E 0x80EA00
+#define SVR_P2040 0x821000
+#define SVR_P2040_E 0x821800
#define SVR_P3041 0x821103
#define SVR_P3041_E 0x821903
#define SVR_P4040 0x820100