ARM: uniphier: add PH1-Pro5 support

The DDR SDRAM initialization code has not been mainlined yet, but
U-Boot proper should work.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

24 files changed, 411 insertions, 1 deletions

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 5afe8a9..0a7d184 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -45,6 +45,7 @@ dtb-$(CONFIG_ARCH_UNIPHIER) += \
 	uniphier-ph1-ld4-ref.dtb \
 	uniphier-ph1-ld6b-ref.dtb \
 	uniphier-ph1-pro4-ref.dtb \
+	uniphier-ph1-pro5-4kbox.dtb \
 	uniphier-ph1-sld3-ref.dtb \
 	uniphier-ph1-sld8-ref.dtb
 dtb-$(CONFIG_ARCH_ZYNQ) += zynq-zc702.dtb \
diff --git a/arch/arm/dts/uniphier-ph1-pro5-4kbox.dts b/arch/arm/dts/uniphier-ph1-pro5-4kbox.dts
new file mode 100644
index 0000000..912bc27
--- /dev/null
+++ b/arch/arm/dts/uniphier-ph1-pro5-4kbox.dts
@@ -0,0 +1,64 @@
+/*
+ * Device Tree Source for UniPhier PH1-Pro5 4KBOX Board (EVB-Pro5-4KBOX-M-V0)
+ *
+ * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/dts-v1/;
+/include/ "uniphier-ph1-pro5.dtsi"
+
+/ {
+	model = "UniPhier PH1-Pro5 4KBOX Board";
+	compatible = "socionext,ph1-pro5-4kbox", "socionext,ph1-pro5";
+
+	memory {
+		device_type = "memory";
+		reg = <0x80000000 0x40000000>;
+	};
+
+	chosen {
+		bootargs = "console=ttyS1,115200";
+		stdout-path = &serial1;
+	};
+
+	aliases {
+		serial1 = &serial1;
+		serial2 = &serial2;
+		i2c0 = &i2c0;
+		i2c5 = &i2c5;
+		i2c6 = &i2c6;
+	};
+};
+
+&serial1 {
+	status = "okay";
+};
+
+&serial2 {
+	status = "okay";
+};
+
+&i2c0 {
+	status = "okay";
+};
+
+/* for U-boot only */
+/ {
+	soc {
+		u-boot,dm-pre-reloc;
+	};
+};
+
+&serial1 {
+	u-boot,dm-pre-reloc;
+};
+
+&pinctrl {
+	u-boot,dm-pre-reloc;
+};
+
+&pinctrl_uart1 {
+	u-boot,dm-pre-reloc;
+};
diff --git a/arch/arm/mach-uniphier/Kconfig b/arch/arm/mach-uniphier/Kconfig
index 2cc5dac..7a62957 100644
--- a/arch/arm/mach-uniphier/Kconfig
+++ b/arch/arm/mach-uniphier/Kconfig
@@ -33,6 +33,15 @@ config ARCH_UNIPHIER_PH1_SLD8
 	help
 	  This enables support for UniPhier PH1-sLD8 SoC.
 
+config ARCH_UNIPHIER_PH1_PRO5
+	bool "UniPhier PH1-Pro5 SoC"
+	select UNIPHIER_SMP
+	depends on !ARCH_UNIPHIER_PH1_SLD3 && \
+		   !ARCH_UNIPHIER_PH1_LD4 && \
+		   !ARCH_UNIPHIER_PH1_SLD8
+	help
+	  This enables support for UniPhier PH1-Pro5 SoC.
+
 config MICRO_SUPPORT_CARD
 	bool "Use Micro Support Card"
 	help
diff --git a/arch/arm/mach-uniphier/board_early_init_f.c b/arch/arm/mach-uniphier/board_early_init_f.c
index cd516c3..fb49272 100644
--- a/arch/arm/mach-uniphier/board_early_init_f.c
+++ b/arch/arm/mach-uniphier/board_early_init_f.c
@@ -41,6 +41,13 @@ int board_early_init_f(void)
 		ph1_ld4_clk_init();
 		break;
 #endif
+#if defined(CONFIG_ARCH_UNIPHIER_PH1_PRO5)
+	case SOC_UNIPHIER_PH1_PRO5:
+		ph1_pro5_pin_init();
+		led_puts("U1");
+		ph1_pro5_clk_init();
+		break;
+#endif
 	default:
 		break;
 	}
diff --git a/arch/arm/mach-uniphier/boards.c b/arch/arm/mach-uniphier/boards.c
index 6a5ea2e..fba8859 100644
--- a/arch/arm/mach-uniphier/boards.c
+++ b/arch/arm/mach-uniphier/boards.c
@@ -59,6 +59,18 @@ static const struct uniphier_board_data ph1_sld8_data = {
 };
 #endif
 
+#if defined(CONFIG_ARCH_UNIPHIER_PH1_PRO5)
+static const struct uniphier_board_data ph1_pro5_data = {
+	.dram_ch0_base  = 0x80000000,
+	.dram_ch0_size  = 0x20000000,
+	.dram_ch0_width = 32,
+	.dram_ch1_base  = 0xa0000000,
+	.dram_ch1_size  = 0x20000000,
+	.dram_ch1_width = 32,
+	.dram_freq      = 1866,
+};
+#endif
+
 struct uniphier_board_id {
 	const char *compatible;
 	const struct uniphier_board_data *param;
@@ -77,6 +89,9 @@ static const struct uniphier_board_id uniphier_boards[] = {
 #if defined(CONFIG_ARCH_UNIPHIER_PH1_SLD8)
 	{ "socionext,ph1-sld8", &ph1_sld8_data, },
 #endif
+#if defined(CONFIG_ARCH_UNIPHIER_PH1_PRO5)
+	{ "socionext,ph1-pro5", &ph1_pro5_data, },
+#endif
 };
 
 const struct uniphier_board_data *uniphier_get_board_param(const void *fdt)
diff --git a/arch/arm/mach-uniphier/boot-mode/Makefile b/arch/arm/mach-uniphier/boot-mode/Makefile
index bd6d0a3..1d2f8b3 100644
--- a/arch/arm/mach-uniphier/boot-mode/Makefile
+++ b/arch/arm/mach-uniphier/boot-mode/Makefile
@@ -4,3 +4,4 @@ obj-$(CONFIG_ARCH_UNIPHIER_PH1_SLD3)	+= boot-mode-ph1-sld3.o
 obj-$(CONFIG_ARCH_UNIPHIER_PH1_LD4)	+= boot-mode-ph1-ld4.o
 obj-$(CONFIG_ARCH_UNIPHIER_PH1_PRO4)	+= boot-mode-ph1-ld4.o
 obj-$(CONFIG_ARCH_UNIPHIER_PH1_SLD8)	+= boot-mode-ph1-ld4.o
+obj-$(CONFIG_ARCH_UNIPHIER_PH1_PRO5)	+= boot-mode-ph1-pro5.o
diff --git a/arch/arm/mach-uniphier/boot-mode/boot-mode-ph1-pro5.c b/arch/arm/mach-uniphier/boot-mode/boot-mode-ph1-pro5.c
new file mode 100644
index 0000000..c68cb59
--- /dev/null
+++ b/arch/arm/mach-uniphier/boot-mode/boot-mode-ph1-pro5.c
@@ -0,0 +1,75 @@
+/*
+ * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <spl.h>
+#include <linux/io.h>
+#include <mach/boot-device.h>
+#include <mach/sbc-regs.h>
+#include <mach/sg-regs.h>
+
+static struct boot_device_info boot_device_table[] = {
+	{BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC  8, EraseSize 128KB, Addr 5)"},
+	{BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, EraseSize 128KB, Addr 5)"},
+	{BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC  8, EraseSize 256KB, Addr 5)"},
+	{BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, EraseSize 256KB, Addr 5)"},
+	{BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC  8, EraseSize 512KB, Addr 5)"},
+	{BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, EraseSize 512KB, Addr 5)"},
+	{BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC  8, EraseSize 128KB, Addr 4)"},
+	{BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, EraseSize 128MB, Addr 4)"},
+	{BOOT_DEVICE_NONE, "Reserved"},
+	{BOOT_DEVICE_NONE, "Reserved"},
+	{BOOT_DEVICE_NONE, "Reserved"},
+	{BOOT_DEVICE_NONE, "Reserved"},
+	{BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC  8, EraseSize 512MB, Addr 5)"},
+	{BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 512KB, Addr 5)"},
+	{BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC  8, EraseSize 128KB, Addr 4)"},
+	{BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 128KB, Addr 4)"},
+	{BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC  8, ONFI,            Addr 5)"},
+	{BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, ONFI,            Addr 5)"},
+	{BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC  8, ONFI,            Addr 4)"},
+	{BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, ONFI,            Addr 4)"},
+	{BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC  8, ONFI,            Addr 5)"},
+	{BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, ONFI,            Addr 5)"},
+	{BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC  8, ONFI,            Addr 4)"},
+	{BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, ONFI,            Addr 4)"},
+	{BOOT_DEVICE_NONE, "Reserved"},
+	{BOOT_DEVICE_MMC1, "eMMC Boot (1.8V)"},
+	{BOOT_DEVICE_NONE, "Reserved"},
+	{BOOT_DEVICE_NONE, "Reserved"},
+	{BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC  8, EraseSize 128MB, Addr 5)"},
+	{BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 128KB, Addr 5)"},
+	{BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC  8, EraseSize 256KB, Addr 5)"},
+	{BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 256KB, Addr 5)"},
+	{ /* sentinel */ }
+};
+
+static int get_boot_mode_sel(void)
+{
+	return (readl(SG_PINMON0) >> 1) & 0x1f;
+}
+
+u32 ph1_pro5_boot_device(void)
+{
+	int boot_mode;
+
+	boot_mode = get_boot_mode_sel();
+
+	return boot_device_table[boot_mode].type;
+}
+
+void ph1_pro5_boot_mode_show(void)
+{
+	int mode_sel, i;
+
+	mode_sel = get_boot_mode_sel();
+
+	puts("Boot Mode Pin:\n");
+
+	for (i = 0; i < ARRAY_SIZE(boot_device_table); i++)
+		printf(" %c %02x %s\n", i == mode_sel ? '*' : ' ', i,
+		       boot_device_table[i].info);
+}
diff --git a/arch/arm/mach-uniphier/boot-mode/boot-mode.c b/arch/arm/mach-uniphier/boot-mode/boot-mode.c
index 71abdef..60329eb 100644
--- a/arch/arm/mach-uniphier/boot-mode/boot-mode.c
+++ b/arch/arm/mach-uniphier/boot-mode/boot-mode.c
@@ -29,6 +29,10 @@ u32 spl_boot_device(void)
 	case SOC_UNIPHIER_PH1_SLD8:
 		return ph1_ld4_boot_device();
 #endif
+#if defined(CONFIG_ARCH_UNIPHIER_PH1_PRO5)
+	case SOC_UNIPHIER_PH1_PRO5:
+		return ph1_pro5_boot_device();
+#endif
 	default:
 		return BOOT_DEVICE_NONE;
 	}
diff --git a/arch/arm/mach-uniphier/clk/Makefile b/arch/arm/mach-uniphier/clk/Makefile
index e6931d6..873c4f7 100644
--- a/arch/arm/mach-uniphier/clk/Makefile
+++ b/arch/arm/mach-uniphier/clk/Makefile
@@ -2,3 +2,4 @@ obj-$(CONFIG_ARCH_UNIPHIER_PH1_SLD3)	+= clk-ph1-ld4.o
 obj-$(CONFIG_ARCH_UNIPHIER_PH1_LD4)	+= clk-ph1-ld4.o
 obj-$(CONFIG_ARCH_UNIPHIER_PH1_PRO4)	+= clk-ph1-pro4.o
 obj-$(CONFIG_ARCH_UNIPHIER_PH1_SLD8)	+= clk-ph1-ld4.o
+obj-$(CONFIG_ARCH_UNIPHIER_PH1_PRO5)	+= clk-ph1-pro5.o
diff --git a/arch/arm/mach-uniphier/clk/clk-ph1-pro5.c b/arch/arm/mach-uniphier/clk/clk-ph1-pro5.c
new file mode 100644
index 0000000..f78edbb
--- /dev/null
+++ b/arch/arm/mach-uniphier/clk/clk-ph1-pro5.c
@@ -0,0 +1,44 @@
+/*
+ * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <linux/io.h>
+#include <mach/init.h>
+#include <mach/sc-regs.h>
+
+void ph1_pro5_clk_init(void)
+{
+	u32 tmp;
+
+	/* deassert reset */
+	tmp = readl(SC_RSTCTRL);
+#ifdef CONFIG_USB_XHCI_UNIPHIER
+	tmp |= SC_RSTCTRL_NRST_USB3B0 | SC_RSTCTRL_NRST_GIO;
+#endif
+#ifdef CONFIG_NAND_DENALI
+	tmp |= SC_RSTCTRL_NRST_NAND;
+#endif
+	writel(tmp, SC_RSTCTRL);
+	readl(SC_RSTCTRL); /* dummy read */
+
+#ifdef CONFIG_USB_XHCI_UNIPHIER
+	tmp = readl(SC_RSTCTRL2);
+	tmp |= SC_RSTCTRL2_NRST_USB3B1;
+	writel(tmp, SC_RSTCTRL2);
+	readl(SC_RSTCTRL2); /* dummy read */
+#endif
+
+	/* privide clocks */
+	tmp = readl(SC_CLKCTRL);
+#ifdef CONFIG_USB_XHCI_UNIPHIER
+	tmp |= SC_CLKCTRL_CEN_USB31 | SC_CLKCTRL_CEN_USB30 |
+		SC_CLKCTRL_CEN_GIO;
+#endif
+#ifdef CONFIG_NAND_DENALI
+	tmp |= SC_CLKCTRL_CEN_NAND;
+#endif
+	writel(tmp, SC_CLKCTRL);
+	readl(SC_CLKCTRL); /* dummy read */
+}
diff --git a/arch/arm/mach-uniphier/cmd_pinmon.c b/arch/arm/mach-uniphier/cmd_pinmon.c
index a61d40e..58c53bf 100644
--- a/arch/arm/mach-uniphier/cmd_pinmon.c
+++ b/arch/arm/mach-uniphier/cmd_pinmon.c
@@ -28,6 +28,11 @@ static int do_pinmon(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 		ph1_ld4_boot_mode_show();
 		break;
 #endif
+#if defined(CONFIG_ARCH_UNIPHIER_PH1_PRO5)
+	case SOC_UNIPHIER_PH1_PRO5:
+		ph1_pro5_boot_mode_show();
+		break;
+#endif
 	default:
 		break;
 	}
diff --git a/arch/arm/mach-uniphier/debug_ll.S b/arch/arm/mach-uniphier/debug_ll.S
index d5ccad3..056f77e 100644
--- a/arch/arm/mach-uniphier/debug_ll.S
+++ b/arch/arm/mach-uniphier/debug_ll.S
@@ -101,6 +101,30 @@ ph1_pro4_end:
 	b		init_uart
 ph1_sld8_end:
 #endif
+#if defined(CONFIG_ARCH_UNIPHIER_PH1_PRO5)
+#define PH1_PRO5_UART_CLK		73728000
+	cmp		r1, #0x2A
+	bne		ph1_pro5_end
+
+	sg_set_pinsel	47, 0, 4, 8, r0, r1	@ TXD0 -> TXD0
+	sg_set_pinsel	49, 0, 4, 8, r0, r1	@ TXD1 -> TXD1
+	sg_set_pinsel	51, 0, 4, 8, r0, r1	@ TXD2 -> TXD2
+	sg_set_pinsel	53, 0, 4, 8, r0, r1	@ TXD3 -> TXD3
+
+	ldr		r0, =SG_LOADPINCTRL
+	mov		r1, #1
+	str		r1, [r0]
+
+	ldr		r0, =SC_CLKCTRL
+	ldr		r1, [r0]
+	orr		r1, r1, #SC_CLKCTRL_CEN_PERI
+	str		r1, [r0]
+
+	ldr		r3, =DIV_ROUND(PH1_PRO5_UART_CLK, 16 * BAUDRATE)
+
+	b		init_uart
+ph1_pro5_end:
+#endif
 
 init_uart:
 	addruart	r0, r1, r2
diff --git a/arch/arm/mach-uniphier/early-clk/Makefile b/arch/arm/mach-uniphier/early-clk/Makefile
index 58af1ad..939795c 100644
--- a/arch/arm/mach-uniphier/early-clk/Makefile
+++ b/arch/arm/mach-uniphier/early-clk/Makefile
@@ -2,3 +2,4 @@ obj-$(CONFIG_ARCH_UNIPHIER_PH1_SLD3)	+= early-clk-ph1-ld4.o
 obj-$(CONFIG_ARCH_UNIPHIER_PH1_LD4)	+= early-clk-ph1-ld4.o
 obj-$(CONFIG_ARCH_UNIPHIER_PH1_PRO4)	+= early-clk-ph1-ld4.o
 obj-$(CONFIG_ARCH_UNIPHIER_PH1_SLD8)	+= early-clk-ph1-ld4.o
+obj-$(CONFIG_ARCH_UNIPHIER_PH1_PRO5)	+= early-clk-ph1-pro5.o
diff --git a/arch/arm/mach-uniphier/early-clk/early-clk-ph1-pro5.c b/arch/arm/mach-uniphier/early-clk/early-clk-ph1-pro5.c
new file mode 100644
index 0000000..007d3b8
--- /dev/null
+++ b/arch/arm/mach-uniphier/early-clk/early-clk-ph1-pro5.c
@@ -0,0 +1,39 @@
+/*
+ * Copyright (C) 2015 Masahiro Yamada <yamada.m@jp.panasonic.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <linux/io.h>
+#include <mach/init.h>
+#include <mach/sc-regs.h>
+
+int ph1_pro5_early_clk_init(const struct uniphier_board_data *bd)
+{
+	u32 tmp;
+
+	/*
+	 * deassert reset
+	 * UMCA2: Ch1 (DDR3)
+	 * UMCA1, UMC31: Ch0 (WIO1)
+	 * UMCA0, UMC30: Ch0 (WIO0)
+	 */
+	tmp = readl(SC_RSTCTRL4);
+	tmp |= SC_RSTCTRL4_NRST_UMCSB | SC_RSTCTRL4_NRST_UMCA2 |
+	       SC_RSTCTRL4_NRST_UMCA1 | SC_RSTCTRL4_NRST_UMCA0 |
+	       SC_RSTCTRL4_NRST_UMC31 | SC_RSTCTRL4_NRST_UMC30;
+	writel(tmp, SC_RSTCTRL4);
+	readl(SC_RSTCTRL); /* dummy read */
+
+	/* privide clocks */
+	tmp = readl(SC_CLKCTRL);
+	tmp |= SC_CLKCTRL_CEN_SBC | SC_CLKCTRL_CEN_PERI;
+	writel(tmp, SC_CLKCTRL);
+	tmp = readl(SC_CLKCTRL4);
+	tmp |= SC_CLKCTRL4_CEN_UMCSB | SC_CLKCTRL4_CEN_UMC1 |
+	       SC_CLKCTRL4_CEN_UMC0;
+	writel(tmp, SC_CLKCTRL4);
+	readl(SC_CLKCTRL4); /* dummy read */
+
+	return 0;
+}
diff --git a/arch/arm/mach-uniphier/include/mach/boot-device.h b/arch/arm/mach-uniphier/include/mach/boot-device.h
index eddb25f..3cbe773 100644
--- a/arch/arm/mach-uniphier/include/mach/boot-device.h
+++ b/arch/arm/mach-uniphier/include/mach/boot-device.h
@@ -14,8 +14,10 @@ struct boot_device_info {
 
 u32 ph1_sld3_boot_device(void);
 u32 ph1_ld4_boot_device(void);
+u32 ph1_pro5_boot_device(void);
 
 void ph1_sld3_boot_mode_show(void);
 void ph1_ld4_boot_mode_show(void);
+void ph1_pro5_boot_mode_show(void);
 
 #endif /* _ASM_BOOT_DEVICE_H_ */
diff --git a/arch/arm/mach-uniphier/include/mach/init.h b/arch/arm/mach-uniphier/include/mach/init.h
index 228cbb1..914182d 100644
--- a/arch/arm/mach-uniphier/include/mach/init.h
+++ b/arch/arm/mach-uniphier/include/mach/init.h
@@ -26,6 +26,7 @@ int ph1_sld3_init(const struct uniphier_board_data *bd);
 int ph1_ld4_init(const struct uniphier_board_data *bd);
 int ph1_pro4_init(const struct uniphier_board_data *bd);
 int ph1_sld8_init(const struct uniphier_board_data *bd);
+int ph1_pro5_init(const struct uniphier_board_data *bd);
 
 #if defined(CONFIG_MICRO_SUPPORT_CARD)
 int ph1_sld3_sbc_init(const struct uniphier_board_data *bd);
@@ -63,6 +64,7 @@ int ph1_sld3_enable_dpll_ssc(const struct uniphier_board_data *bd);
 int ph1_ld4_enable_dpll_ssc(const struct uniphier_board_data *bd);
 
 int ph1_ld4_early_clk_init(const struct uniphier_board_data *bd);
+int ph1_pro5_early_clk_init(const struct uniphier_board_data *bd);
 
 int ph1_sld3_early_pin_init(const struct uniphier_board_data *bd);
 
@@ -74,9 +76,11 @@ void ph1_sld3_pin_init(void);
 void ph1_ld4_pin_init(void);
 void ph1_pro4_pin_init(void);
 void ph1_sld8_pin_init(void);
+void ph1_pro5_pin_init(void);
 
 void ph1_ld4_clk_init(void);
 void ph1_pro4_clk_init(void);
+void ph1_pro5_clk_init(void);
 
 #define pr_err(fmt, args...)	printf(fmt, ##args)
 
diff --git a/arch/arm/mach-uniphier/include/mach/sc-regs.h b/arch/arm/mach-uniphier/include/mach/sc-regs.h
index 9d697b1..903e405 100644
--- a/arch/arm/mach-uniphier/include/mach/sc-regs.h
+++ b/arch/arm/mach-uniphier/include/mach/sc-regs.h
@@ -15,6 +15,10 @@
 #define SC_BASE_ADDR			0x61840000
 #endif
 
+#define SC_DPLLOSCCTRL			(SC_BASE_ADDR | 0x1110)
+#define SC_DPLLOSCCTRL_DPLLST		(0x1 << 1)
+#define SC_DPLLOSCCTRL_DPLLEN		(0x1 << 0)
+
 #define SC_DPLLCTRL			(SC_BASE_ADDR | 0x1200)
 #define SC_DPLLCTRL_SSC_EN		(0x1 << 31)
 #define SC_DPLLCTRL_FOUTMODE_MASK        (0xf << 16)
@@ -43,6 +47,7 @@
 #define SC_RSTCTRL_NRST_ETHER		(0x1 << 12)
 #define SC_RSTCTRL_NRST_STDMAC		(0x1 << 10)
 #define SC_RSTCTRL_NRST_GIO		(0x1 <<  6)
+/* Pro4 or older */
 #define SC_RSTCTRL_NRST_UMC1		(0x1 <<  5)
 #define SC_RSTCTRL_NRST_UMC0		(0x1 <<  4)
 #define SC_RSTCTRL_NRST_NAND		(0x1 <<  2)
@@ -53,6 +58,15 @@
 
 #define SC_RSTCTRL3			(SC_BASE_ADDR | 0x2008)
 
+/* Pro5 or newer */
+#define SC_RSTCTRL4			(SC_BASE_ADDR | 0x200c)
+#define SC_RSTCTRL4_NRST_UMCSB		(0x1 << 12)	/* UMC system bus */
+#define SC_RSTCTRL4_NRST_UMCA2		(0x1 << 10)	/* UMC ch2 standby */
+#define SC_RSTCTRL4_NRST_UMCA1		(0x1 <<  9)	/* UMC ch1 standby */
+#define SC_RSTCTRL4_NRST_UMCA0		(0x1 <<  8)	/* UMC ch0 standby */
+#define SC_RSTCTRL4_NRST_UMC31		(0x1 <<  5)	/* UMC ch1 */
+#define SC_RSTCTRL4_NRST_UMC30		(0x1 <<  4)	/* UMC ch0 */
+
 #define SC_CLKCTRL			(SC_BASE_ADDR | 0x2104)
 #define SC_CLKCTRL_CEN_USB31		(0x1 << 17)	/* USB3 #1 */
 #define SC_CLKCTRL_CEN_USB30		(0x1 << 16)	/* USB3 #0 */
@@ -60,11 +74,18 @@
 #define SC_CLKCTRL_CEN_MIO		(0x1 << 11)
 #define SC_CLKCTRL_CEN_STDMAC		(0x1 << 10)
 #define SC_CLKCTRL_CEN_GIO		(0x1 <<  6)
+/* Pro4 or older */
 #define SC_CLKCTRL_CEN_UMC		(0x1 <<  4)
 #define SC_CLKCTRL_CEN_NAND		(0x1 <<  2)
 #define SC_CLKCTRL_CEN_SBC		(0x1 <<  1)
 #define SC_CLKCTRL_CEN_PERI		(0x1 <<  0)
 
+/* Pro5 or newer */
+#define SC_CLKCTRL4			(SC_BASE_ADDR | 0x210c)
+#define SC_CLKCTRL4_CEN_UMCSB		(0x1 << 12)	/* UMC system bus */
+#define SC_CLKCTRL4_CEN_UMC1		(0x1 <<  1)	/* UMC ch1 */
+#define SC_CLKCTRL4_CEN_UMC0		(0x1 <<  0)	/* UMC ch0 */
+
 /* System reset control register */
 #define SC_IRQTIMSET			(SC_BASE_ADDR | 0x3000)
 #define SC_SLFRSTSEL			(SC_BASE_ADDR | 0x3010)
diff --git a/arch/arm/mach-uniphier/include/mach/sg-regs.h b/arch/arm/mach-uniphier/include/mach/sg-regs.h
index d8239f2..168b35e 100644
--- a/arch/arm/mach-uniphier/include/mach/sg-regs.h
+++ b/arch/arm/mach-uniphier/include/mach/sg-regs.h
@@ -59,7 +59,7 @@
 /* Pin Control */
 #define SG_PINCTRL_BASE			(SG_CTRL_BASE | 0x1000)
 
-/* Only for PH1-Pro4 */
+/* PH1-Pro4, PH1-Pro5 */
 #define SG_LOADPINCTRL			(SG_CTRL_BASE | 0x1700)
 
 /* Input Enable */
diff --git a/arch/arm/mach-uniphier/init/Makefile b/arch/arm/mach-uniphier/init/Makefile
index dd9804d..1524a8d 100644
--- a/arch/arm/mach-uniphier/init/Makefile
+++ b/arch/arm/mach-uniphier/init/Makefile
@@ -4,3 +4,4 @@ obj-$(CONFIG_ARCH_UNIPHIER_PH1_SLD3)	+= init-ph1-sld3.o
 obj-$(CONFIG_ARCH_UNIPHIER_PH1_LD4)	+= init-ph1-ld4.o
 obj-$(CONFIG_ARCH_UNIPHIER_PH1_PRO4)	+= init-ph1-pro4.o
 obj-$(CONFIG_ARCH_UNIPHIER_PH1_SLD8)	+= init-ph1-sld8.o
+obj-$(CONFIG_ARCH_UNIPHIER_PH1_PRO5)	+= init-ph1-pro5.o
diff --git a/arch/arm/mach-uniphier/init/init-ph1-pro5.c b/arch/arm/mach-uniphier/init/init-ph1-pro5.c
new file mode 100644
index 0000000..92b3f21
--- /dev/null
+++ b/arch/arm/mach-uniphier/init/init-ph1-pro5.c
@@ -0,0 +1,42 @@
+/*
+ * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <spl.h>
+#include <linux/compiler.h>
+#include <mach/init.h>
+#include <mach/micro-support-card.h>
+
+int ph1_pro5_init(const struct uniphier_board_data *bd)
+{
+	ph1_pro4_sbc_init(bd);
+
+	support_card_reset();
+
+	support_card_init();
+
+	led_puts("L0");
+
+	memconf_init(bd);
+
+	led_puts("L1");
+
+	ph1_pro5_early_clk_init(bd);
+
+	led_puts("L2");
+
+	led_puts("L3");
+
+#ifdef CONFIG_SPL_SERIAL_SUPPORT
+	preloader_console_init();
+#endif
+
+	led_puts("L4");
+
+	led_puts("L5");
+
+	return 0;
+}
diff --git a/arch/arm/mach-uniphier/init/init.c b/arch/arm/mach-uniphier/init/init.c
index 316be02..2649e6c 100644
--- a/arch/arm/mach-uniphier/init/init.c
+++ b/arch/arm/mach-uniphier/init/init.c
@@ -40,6 +40,11 @@ void spl_board_init(void)
 		ph1_sld8_init(param);
 		break;
 #endif
+#if defined(CONFIG_ARCH_UNIPHIER_PH1_PRO5)
+	case SOC_UNIPHIER_PH1_PRO5:
+		ph1_pro5_init(param);
+		break;
+#endif
 	default:
 		break;
 	}
diff --git a/arch/arm/mach-uniphier/pinctrl/Makefile b/arch/arm/mach-uniphier/pinctrl/Makefile
index 542c670..a785245 100644
--- a/arch/arm/mach-uniphier/pinctrl/Makefile
+++ b/arch/arm/mach-uniphier/pinctrl/Makefile
@@ -2,3 +2,4 @@ obj-$(CONFIG_ARCH_UNIPHIER_PH1_SLD3)	+= pinctrl-ph1-sld3.o
 obj-$(CONFIG_ARCH_UNIPHIER_PH1_LD4)	+= pinctrl-ph1-ld4.o
 obj-$(CONFIG_ARCH_UNIPHIER_PH1_PRO4)	+= pinctrl-ph1-pro4.o
 obj-$(CONFIG_ARCH_UNIPHIER_PH1_SLD8)	+= pinctrl-ph1-sld8.o
+obj-$(CONFIG_ARCH_UNIPHIER_PH1_PRO5)	+= pinctrl-ph1-pro5.o
diff --git a/arch/arm/mach-uniphier/pinctrl/pinctrl-ph1-pro5.c b/arch/arm/mach-uniphier/pinctrl/pinctrl-ph1-pro5.c
new file mode 100644
index 0000000..a6cc082
--- /dev/null
+++ b/arch/arm/mach-uniphier/pinctrl/pinctrl-ph1-pro5.c
@@ -0,0 +1,43 @@
+/*
+ * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <linux/io.h>
+#include <mach/init.h>
+#include <mach/sg-regs.h>
+
+void ph1_pro5_pin_init(void)
+{
+	/* Comment format:    PAD Name -> Function Name */
+
+#ifdef CONFIG_NAND_DENALI
+	sg_set_pinsel(19, 0, 4, 8);	/* XNFRE  -> XNFRE */
+	sg_set_pinsel(20, 0, 4, 8);	/* XNFWE  -> XNFWE */
+	sg_set_pinsel(21, 0, 4, 8);	/* NFALE  -> NFALE */
+	sg_set_pinsel(22, 0, 4, 8);	/* NFCLE  -> NFCLE */
+	sg_set_pinsel(23, 0, 4, 8);	/* XNFWP  -> XNFWP */
+	sg_set_pinsel(24, 0, 4, 8);	/* XNFCE0 -> XNFCE0 */
+	sg_set_pinsel(25, 0, 4, 8);	/* NRYBY0 -> NRYBY0 */
+	sg_set_pinsel(26, 0, 4, 8);	/* XNFCE1 -> XNFCE1 */
+	sg_set_pinsel(27, 0, 4, 8);	/* NRYBY1 -> NRYBY1 */
+	sg_set_pinsel(28, 0, 4, 8);	/* NFD0   -> NFD0 */
+	sg_set_pinsel(29, 0, 4, 8);	/* NFD1   -> NFD1 */
+	sg_set_pinsel(30, 0, 4, 8);	/* NFD2   -> NFD2 */
+	sg_set_pinsel(31, 0, 4, 8);	/* NFD3   -> NFD3 */
+	sg_set_pinsel(32, 0, 4, 8);	/* NFD4   -> NFD4 */
+	sg_set_pinsel(33, 0, 4, 8);	/* NFD5   -> NFD5 */
+	sg_set_pinsel(34, 0, 4, 8);	/* NFD6   -> NFD6 */
+	sg_set_pinsel(35, 0, 4, 8);	/* NFD7   -> NFD7 */
+#endif
+
+#ifdef CONFIG_USB_XHCI_UNIPHIER
+	sg_set_pinsel(124, 0, 4, 8);	/* USB0VBUS -> USB0VBUS */
+	sg_set_pinsel(125, 0, 4, 8);	/* USB0OD   -> USB0OD */
+	sg_set_pinsel(126, 0, 4, 8);	/* USB1VBUS -> USB1VBUS */
+	sg_set_pinsel(127, 0, 4, 8);	/* USB1OD   -> USB1OD */
+#endif
+
+	writel(1, SG_LOADPINCTRL);
+}
diff --git a/arch/arm/mach-uniphier/sbc/Makefile b/arch/arm/mach-uniphier/sbc/Makefile
index 68ffd1c..2c5fd1a 100644
--- a/arch/arm/mach-uniphier/sbc/Makefile
+++ b/arch/arm/mach-uniphier/sbc/Makefile
@@ -2,3 +2,4 @@ obj-$(CONFIG_ARCH_UNIPHIER_PH1_SLD3)	+= sbc-ph1-sld3.o
 obj-$(CONFIG_ARCH_UNIPHIER_PH1_LD4)	+= sbc-ph1-ld4.o
 obj-$(CONFIG_ARCH_UNIPHIER_PH1_PRO4)	+= sbc-ph1-pro4.o
 obj-$(CONFIG_ARCH_UNIPHIER_PH1_SLD8)	+= sbc-ph1-ld4.o
+obj-$(CONFIG_ARCH_UNIPHIER_PH1_PRO5)	+= sbc-ph1-pro4.o