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authorLinus Walleij <linus.walleij@linaro.org>2015-03-09 10:53:21 +0100
committerTom Rini <trini@konsulko.com>2015-03-09 11:13:29 -0400
commit23b5877c64562a314f8d8c60d0066cd346f2d886 (patch)
tree637ae686c8cda5a7c7d28216bf7d4c1f79f0f945 /arch
parent671fa63e79053c33456c198c1e0f74262b0b2548 (diff)
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armv8/vexpress64: make multientry conditional
While the Freescale ARMv8 board LS2085A will enter U-Boot both on a master and a secondary (slave) CPU, this is not the common behaviour on ARMv8 platforms. The norm is that U-Boot is entered from the master CPU only, while the other CPUs are kept in WFI (wait for interrupt) state. The code determining which CPU we are running on is using the MPIDR register, but the definition of that register varies with platform to some extent, and handling multi-cluster platforms (such as the Juno) will become cumbersome. It is better to only enable the multiple entry code on machines that actually need it and disable it by default. Make the single entry default and add a special ARMV8_MULTIENTRY KConfig option to be used by the platforms that need multientry and set it for the LS2085A. Delete all use of the CPU_RELEASE_ADDR from the Vexpress64 boards as it is just totally unused and misleading, and make it conditional in the generic start.S code. This makes the Juno platform start U-Boot properly. Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/Kconfig4
-rw-r--r--arch/arm/cpu/armv8/Kconfig6
-rw-r--r--arch/arm/cpu/armv8/start.S19
-rw-r--r--arch/arm/include/asm/macro.h8
4 files changed, 33 insertions, 4 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 72e7981..b9ebee1 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -641,10 +641,12 @@ config TARGET_VEXPRESS64_JUNO
config TARGET_LS2085A_EMU
bool "Support ls2085a_emu"
select ARM64
+ select ARMV8_MULTIENTRY
config TARGET_LS2085A_SIMU
bool "Support ls2085a_simu"
select ARM64
+ select ARMV8_MULTIENTRY
config TARGET_LS1021AQDS
bool "Support ls1021aqds"
@@ -757,6 +759,8 @@ source "arch/arm/cpu/armv7/zynq/Kconfig"
source "arch/arm/cpu/armv7/Kconfig"
+source "arch/arm/cpu/armv8/Kconfig"
+
source "board/aristainetos/Kconfig"
source "board/BuR/kwb/Kconfig"
source "board/BuR/tseries/Kconfig"
diff --git a/arch/arm/cpu/armv8/Kconfig b/arch/arm/cpu/armv8/Kconfig
new file mode 100644
index 0000000..4cd84b0
--- /dev/null
+++ b/arch/arm/cpu/armv8/Kconfig
@@ -0,0 +1,6 @@
+if ARM64
+
+config ARMV8_MULTIENTRY
+ boolean "Enable multiple CPUs to enter into U-boot"
+
+endif
diff --git a/arch/arm/cpu/armv8/start.S b/arch/arm/cpu/armv8/start.S
index 4b11aa4..df80a4e 100644
--- a/arch/arm/cpu/armv8/start.S
+++ b/arch/arm/cpu/armv8/start.S
@@ -77,6 +77,7 @@ reset:
/* Processor specific initialization */
bl lowlevel_init
+#ifdef CONFIG_ARMV8_MULTIENTRY
branch_if_master x0, x1, master_cpu
/*
@@ -88,11 +89,10 @@ slave_cpu:
ldr x0, [x1]
cbz x0, slave_cpu
br x0 /* branch to the given address */
-
- /*
- * Master CPU
- */
master_cpu:
+ /* On the master CPU */
+#endif /* CONFIG_ARMV8_MULTIENTRY */
+
bl _main
/*-----------------------------------------------------------------------*/
@@ -100,6 +100,15 @@ master_cpu:
WEAK(lowlevel_init)
mov x29, lr /* Save LR */
+#ifndef CONFIG_ARMV8_MULTIENTRY
+ /*
+ * For single-entry systems the lowlevel init is very simple.
+ */
+ ldr x0, =GICD_BASE
+ bl gic_init_secure
+
+#else /* CONFIG_ARMV8_MULTIENTRY is set */
+
#if defined(CONFIG_GICV2) || defined(CONFIG_GICV3)
branch_if_slave x0, 1f
ldr x0, =GICD_BASE
@@ -137,6 +146,8 @@ WEAK(lowlevel_init)
bl armv8_switch_to_el1
#endif
+#endif /* CONFIG_ARMV8_MULTIENTRY */
+
2:
mov lr, x29 /* Restore LR */
ret
diff --git a/arch/arm/include/asm/macro.h b/arch/arm/include/asm/macro.h
index 1c8c425..3b3146a 100644
--- a/arch/arm/include/asm/macro.h
+++ b/arch/arm/include/asm/macro.h
@@ -78,6 +78,8 @@ lr .req x30
* choose processor with all zero affinity value as the master.
*/
.macro branch_if_slave, xreg, slave_label
+#ifdef CONFIG_ARMV8_MULTIENTRY
+ /* NOTE: MPIDR handling will be erroneous on multi-cluster machines */
mrs \xreg, mpidr_el1
tst \xreg, #0xff /* Test Affinity 0 */
b.ne \slave_label
@@ -90,6 +92,7 @@ lr .req x30
lsr \xreg, \xreg, #16
tst \xreg, #0xff /* Test Affinity 3 */
b.ne \slave_label
+#endif
.endm
/*
@@ -97,12 +100,17 @@ lr .req x30
* choose processor with all zero affinity value as the master.
*/
.macro branch_if_master, xreg1, xreg2, master_label
+#ifdef CONFIG_ARMV8_MULTIENTRY
+ /* NOTE: MPIDR handling will be erroneous on multi-cluster machines */
mrs \xreg1, mpidr_el1
lsr \xreg2, \xreg1, #32
lsl \xreg1, \xreg1, #40
lsr \xreg1, \xreg1, #40
orr \xreg1, \xreg1, \xreg2
cbz \xreg1, \master_label
+#else
+ b \master_label
+#endif
.endm
.macro armv8_switch_to_el2_m, xreg1