diff options
author | Peng Fan <peng.fan@nxp.com> | 2016-02-19 15:18:06 +0800 |
---|---|---|
committer | Ye Li <ye.li@nxp.com> | 2017-03-14 21:27:09 +0800 |
commit | 1da582f58b195a745cbc7ab4ad7a3f6d2e71f610 (patch) | |
tree | be72b3ecf45c8815606cc15515f63a809f5eabab /arch | |
parent | bfbeae690ac385dfd24056dd7b12705e4d4902d7 (diff) | |
download | u-boot-imx-1da582f58b195a745cbc7ab4ad7a3f6d2e71f610.zip u-boot-imx-1da582f58b195a745cbc7ab4ad7a3f6d2e71f610.tar.gz u-boot-imx-1da582f58b195a745cbc7ab4ad7a3f6d2e71f610.tar.bz2 |
MLK-12416-4: imx: mx6: update imx-regs.h
Update imx-regs.h to align with 2016.03
Signed-off-by: Peng Fan <peng.fan@nxp.com>
(cherry picked from commit 9bbd54e44ae1f0868d3f0dd34975e76606b0a5e8)
Diffstat (limited to 'arch')
-rw-r--r-- | arch/arm/include/asm/arch-mx6/imx-regs.h | 132 |
1 files changed, 119 insertions, 13 deletions
diff --git a/arch/arm/include/asm/arch-mx6/imx-regs.h b/arch/arm/include/asm/arch-mx6/imx-regs.h index 6727c56..7165a15 100644 --- a/arch/arm/include/asm/arch-mx6/imx-regs.h +++ b/arch/arm/include/asm/arch-mx6/imx-regs.h @@ -121,7 +121,7 @@ #define MMDC1_ARB_END_ADDR 0xFFFFFFFF #endif -#ifndef CONFIG_MX6SX +#if (!(defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL) || defined(CONFIG_MX6SLL))) #define IPU_SOC_BASE_ADDR IPU1_ARB_BASE_ADDR #define IPU_SOC_OFFSET 0x00200000 #endif @@ -153,16 +153,25 @@ #ifndef CONFIG_MX6SX #define ECSPI5_BASE_ADDR (ATZ1_BASE_ADDR + 0x18000) #endif -#define UART1_IPS_BASE_ADDR (ATZ1_BASE_ADDR + 0x20000) + #define UART1_BASE (ATZ1_BASE_ADDR + 0x20000) #define ESAI1_BASE_ADDR (ATZ1_BASE_ADDR + 0x24000) -#define UART8_BASE (ATZ1_BASE_ADDR + 0x24000) + +#if defined(CONFIG_MX6UL) +#define SAI1_BASE_ADDR (ATZ1_BASE_ADDR + 0x28000) +#define SAI2_BASE_ADDR (ATZ1_BASE_ADDR + 0x2C000) +#define SAI3_BASE_ADDR (ATZ1_BASE_ADDR + 0x30000) +#else #define SSI1_BASE_ADDR (ATZ1_BASE_ADDR + 0x28000) #define SSI2_BASE_ADDR (ATZ1_BASE_ADDR + 0x2C000) #define SSI3_BASE_ADDR (ATZ1_BASE_ADDR + 0x30000) +#endif #define ASRC_BASE_ADDR (ATZ1_BASE_ADDR + 0x34000) -#ifndef CONFIG_MX6SX +#if defined(CONFIG_MX6UL) +#define TOUCH_CTRL_BASE_ADDR (ATZ1_BASE_ADDR + 0x40000) +#define BEE_BASE_ADDR (ATZ1_BASE_ADDR + 0x44000) +#elif !defined(CONFIG_MX6SX) #define SPBA_BASE_ADDR (ATZ1_BASE_ADDR + 0x3C000) #define VPU_BASE_ADDR (ATZ1_BASE_ADDR + 0x40000) #endif @@ -184,8 +193,13 @@ #define GPIO4_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x28000) #define GPIO5_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x2C000) #define MX6UL_SNVS_LP_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x30000) +#if defined(CONFIG_MX6UL) +#define SNVS_LP_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x30000) +#define ENET2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x34000) +#else #define GPIO6_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x30000) #define GPIO7_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x34000) +#endif #define KPP_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x38000) #define WDOG1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x3C000) #define WDOG2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x40000) @@ -210,6 +224,7 @@ #define CSI_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x64000) #define SIPIX_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x68000) #define SDMA_PORT_HOST_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x6C000) +#define EPDC_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x74000) #elif defined(CONFIG_MX6SX) #define CANFD1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x68000) #define SDMA_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x6C000) @@ -217,10 +232,19 @@ #define SEMAPHORE1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x74000) #define SEMAPHORE2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x78000) #define RDC_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x7C000) + +#elif defined(CONFIG_MX6UL) +#define GPT2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x68000) +#define SDMA_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x6C000) +#define PWM5_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x70000) +#define PWM6_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x74000) +#define PWM7_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x78000) +#define PWM8_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x7C000) #else #define DCIC1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x64000) #define DCIC2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x68000) #define DMA_REQ_PORT_HOST_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x6C000) +#define EPDC_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x74000) #endif #define MX6SL_LCDIF_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x78000) @@ -230,8 +254,14 @@ #define AIPS2_OFF_BASE_ADDR (ATZ2_BASE_ADDR + 0x80000) #define AIPS3_ON_BASE_ADDR (ATZ3_BASE_ADDR + 0x7C000) #define AIPS3_OFF_BASE_ADDR (ATZ3_BASE_ADDR + 0x80000) + +#if defined(CONFIG_MX6UL) +#define CAAM_BASE_ADDR (ATZ2_BASE_ADDR + 0x40000) +#define ARM_BASE_ADDR (ATZ2_BASE_ADDR) +#else #define CAAM_BASE_ADDR (ATZ2_BASE_ADDR) #define ARM_BASE_ADDR (ATZ2_BASE_ADDR + 0x40000) +#endif #define CONFIG_SYS_FSL_SEC_OFFSET 0 #define CONFIG_SYS_FSL_SEC_ADDR (CAAM_BASE_ADDR + \ @@ -247,6 +277,8 @@ #define ENET_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x8000) #ifdef CONFIG_MX6SL #define MSHC_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0xC000) +#elif defined(CONFIG_MX6UL) +#define SIM1_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0xC000) #else #define MLB_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0xC000) #endif @@ -255,6 +287,9 @@ #define USDHC2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x14000) #define USDHC3_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x18000) #define USDHC4_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x1C000) + +#define MX6UL_ADC1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x18000) +#define MX6UL_ADC2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x1C000) #define I2C1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x20000) #define I2C2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x24000) #define I2C3_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x28000) @@ -274,12 +309,16 @@ #define WEIM_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x38000) #define OCOTP_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x3C000) #define CSU_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x40000) -#ifdef CONFIG_MX6SLL +#if defined(CONFIG_MX6UL) +#define CSI_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x44000) +#define PXP_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x4C000) +#elif defined(CONFIG_MX6SLL) #define IOMUXC_GPR_SNVS_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x44000) #define IOMUXC_SNVS_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x48000) -#endif +#else #define IP2APB_PERFMON1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x44000) #define IP2APB_PERFMON2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x48000) +#endif #define MX6UL_LCDIF1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x48000) #define MX6ULL_LCDIF1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x48000) #ifdef CONFIG_MX6SX @@ -290,7 +329,9 @@ #define IP2APB_TZASC1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x50000) #ifdef CONFIG_MX6UL #define QSPI0_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x60000) -#define UART6_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x7C000) +#define SYSCNT_RD_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x54000) +#define SYSCNT_CMP_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x58000) +#define SYSCNT_CTRL_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x5C000) #elif defined(CONFIG_MX6SX) #define SAI1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x54000) #define AUDMUX_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x58000) @@ -308,11 +349,20 @@ #define UART3_BASE (AIPS2_OFF_BASE_ADDR + 0x6C000) #define UART4_BASE (AIPS2_OFF_BASE_ADDR + 0x70000) #define UART5_BASE (AIPS2_OFF_BASE_ADDR + 0x74000) +/* i.MX6SLL */ +#define MTR_MASTER_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x7C000) +/* i.MX6SX/UL */ #define I2C4_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x78000) +/* i.MX6UL */ +#define MX6UL_UART6_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x7C000) #define IP2APB_USBPHY1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x78000) #define IP2APB_USBPHY2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x7C000) -/* i.MX6SLL */ -#define MTR_MASTER_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x7C000) + +#define OTG_BASE_ADDR USB_BASE_ADDR + +#if defined(CONFIG_MX6UL) +#define SCTR_BASE_ADDR SYSCNT_CTRL_IPS_BASE_ADDR +#endif #ifdef CONFIG_MX6SX #define GIS_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x04000) @@ -325,14 +375,13 @@ #define VDEC_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x2C000) #define SPBA_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x3C000) #define AIPS3_CONFIG_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x7C000) -#define ADC1_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x80000) -#define ADC2_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x84000) +#define MX6SX_ADC1_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x80000) +#define MX6SX_ADC2_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x84000) #define ECSPI5_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x8C000) #define HS_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x90000) #define MU_MCU_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x94000) #define CANFD_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x98000) #define MU_DSP_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x9C000) -#define UART6_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0xA0000) #define PWM5_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0xA4000) #define PWM6_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0xA8000) #define PWM7_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0xAC000) @@ -350,6 +399,7 @@ #define LCDIF2_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x24000) #define MX6SX_LCDIF1_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x20000) #define MX6SX_WDOG3_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x88000) +#define MX6SX_UART6_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0xA0000) #if !(defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL) || \ defined(CONFIG_MX6SLL) || defined(CONFIG_MX6SL)) @@ -358,13 +408,14 @@ #define IRAM_SIZE 0x00020000 #endif #define FEC_QUIRK_ENET_MAC +#define SNVS_LPGPR 0x68 #include <asm/imx-common/regs-lcdif.h> #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__)) #include <asm/types.h> /* only for i.MX6SX/UL */ -#define WDOG3_BASE_ADDR ((is_mx6ul() ? \ +#define WDOG3_BASE_ADDR (((is_mx6ul() || is_mx6ull()) ? \ MX6UL_WDOG3_BASE_ADDR : MX6SX_WDOG3_BASE_ADDR)) #define LCDIF1_BASE_ADDR ((is_cpu_type(MXC_CPU_MX6SLL)) ? \ MX6SLL_LCDIF_BASE_ADDR : \ @@ -374,6 +425,10 @@ MX6UL_LCDIF1_BASE_ADDR : \ ((is_mx6ull()) ? \ MX6ULL_LCDIF1_BASE_ADDR : MX6SX_LCDIF1_BASE_ADDR))) +#define UART6_BASE_ADDR ((is_mx6ul() || is_mx6ull()) ? \ + MX6UL_UART6_BASE_ADDR : MX6SX_UART6_BASE_ADDR) + +#define MXS_LCDIF_BASE LCDIF1_BASE_ADDR extern void imx_get_mac_from_fuse(int dev_id, unsigned char *mac); @@ -571,7 +626,12 @@ struct iomuxc { #if (defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL)) u8 reserved[0x4000]; #endif + +#ifdef CONFIG_MX6UL + u32 gpr[15]; +#else u32 gpr[14]; +#endif }; struct gpc { @@ -654,6 +714,12 @@ struct gpc { #define IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0 (IOMUXC_GPR2_MODE_ENABLED_DI0<<IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET) #define IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI1 (IOMUXC_GPR2_MODE_ENABLED_DI1<<IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET) +#define IMX6SX_GPR5_CSI1_MUX_CTRL_MASK (0x3 << 4) +#define IMX6SX_GPR5_CSI1_MUX_CTRL_EXT_PIN (0x0 << 4) +#define IMX6SX_GPR5_CSI1_MUX_CTRL_CVD (0x1 << 4) +#define IMX6SX_GPR5_CSI1_MUX_CTRL_VDAC_TO_CSI (0x2 << 4) +#define IMX6SX_GPR5_CSI1_MUX_CTRL_GND (0x3 << 4) + /* ECSPI registers */ struct cspi_regs { u32 rxdata; @@ -684,7 +750,12 @@ struct cspi_regs { #define MXC_CSPICTRL_RXOVF (1 << 6) #define MXC_CSPIPERIOD_32KHZ (1 << 15) #define MAX_SPI_BYTES 32 +#if defined(CONFIG_MX6DL) || defined(CONFIG_MX6UL) || \ + defined(CONFIG_MX6SLL) || defined(CONFIG_MX6SL) +#define SPI_MAX_NUM 3 +#else #define SPI_MAX_NUM 4 +#endif /* Bit position inside CTRL register to be associated with SS */ #define MXC_CSPICTRL_CHAN 18 @@ -710,6 +781,8 @@ struct cspi_regs { ECSPI5_BASE_ADDR #endif +#define ANATOP_PLL_VIDEO 0xA0 + struct ocotp_regs { u32 ctrl; u32 ctrl_set; @@ -959,6 +1032,25 @@ struct anatop_regs { #define ANATOP_PFD_CLKGATE_SHIFT(n) (7+((n)*8)) #define ANATOP_PFD_CLKGATE_MASK(n) (1<<ANATOP_PFD_CLKGATE_SHIFT(n)) +struct iomuxc_gpr_base_regs { +#if defined(CONFIG_MX6UL) + u32 gpr[15]; /* 0x000 */ +#else + u32 gpr[14]; /* 0x000 */ +#endif +}; + +struct iomuxc_base_regs { +#if !(defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL)) + u32 gpr[14]; /* 0x000 */ +#endif + u32 obsrv[5]; /* 0x038 */ + u32 swmux_ctl[197]; /* 0x04c */ + u32 swpad_ctl[250]; /* 0x360 */ + u32 swgrp[26]; /* 0x748 */ + u32 daisy[104]; /* 0x7b0..94c */ +}; + struct wdog_regs { u16 wcr; /* Control */ u16 wsr; /* Service */ @@ -983,5 +1075,19 @@ struct pwm_regs { u32 pr; u32 cnr; }; + +struct dbg_monitor_regs { + u32 ctrl[4]; /* Control */ + u32 master_en[4]; /* Master enable */ + u32 irq[4]; /* IRQ */ + u32 trap_addr_low[4]; /* Trap address low */ + u32 trap_addr_high[4]; /* Trap address high */ + u32 trap_id[4]; /* Trap ID */ + u32 snvs_addr[4]; /* SNVS address */ + u32 snvs_data[4]; /* SNVS data */ + u32 snvs_info[4]; /* SNVS info */ + u32 version[4]; /* Version */ +}; + #endif /* __ASSEMBLER__*/ #endif /* __ASM_ARCH_MX6_IMX_REGS_H__ */ |