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authorWolfgang Denk <wd@denx.de>2011-08-02 21:45:45 +0200
committerWolfgang Denk <wd@denx.de>2011-08-02 21:45:45 +0200
commitcc4e6d25561b1aaa8501fa6017a0d17fd4f92ed6 (patch)
treec2f889a257e55ae81842b74ee57ef2b16e8c685a /arch
parent982db890e8ef5afa142f9519f44316086e4c2954 (diff)
parent92bbd64e39299337dbc9ee35053e38c9b1718966 (diff)
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Merge branch 'master' of git://git.denx.de/u-boot-mips
* 'master' of git://git.denx.de/u-boot-mips: README: update MIPS related informations MIPS: make cache operation mode configurable MIPS: rename INFINEON_EBU_BOOTCFG to CONFIG_SYS_XWAY_EBU_BOOTFG MIPS: INCA-IP: rename inca-swap-bytes host tool
Diffstat (limited to 'arch')
-rw-r--r--arch/mips/cpu/mips32/start.S19
1 files changed, 15 insertions, 4 deletions
diff --git a/arch/mips/cpu/mips32/start.S b/arch/mips/cpu/mips32/start.S
index 5d7467d..9c1b2f7 100644
--- a/arch/mips/cpu/mips32/start.S
+++ b/arch/mips/cpu/mips32/start.S
@@ -27,6 +27,10 @@
#include <asm/regdef.h>
#include <asm/mipsregs.h>
+#ifndef CONFIG_SYS_MIPS_CACHE_MODE
+#define CONFIG_SYS_MIPS_CACHE_MODE CONF_CM_CACHABLE_NONCOHERENT
+#endif
+
/*
* For the moment disable interrupts, mark the kernel mode and
* set ST0_KX so that the CPU does not spit fire when using
@@ -64,9 +68,16 @@
_start:
RVECENT(reset,0) # U-boot entry point
RVECENT(reset,1) # software reboot
-#ifdef CONFIG_INCA_IP
- .word INFINEON_EBU_BOOTCFG # EBU init code, fetched during
- .word 0x00000000 # booting phase of the flash
+#ifdef CONFIG_SYS_XWAY_EBU_BOOTCFG
+ /*
+ * Almost all Lantiq XWAY SoC devices have an external bus unit (EBU) to
+ * access external NOR flashes. If the board boots from NOR flash the
+ * internal BootROM does a blind read at address 0xB0000010 to read the
+ * initial configuration for that EBU in order to access the flash
+ * device with correct parameters. This config option is board-specific.
+ */
+ .word CONFIG_SYS_XWAY_EBU_BOOTCFG
+ .word 0x00000000
#else
RVECENT(romReserved,2)
#endif
@@ -242,7 +253,7 @@ reset:
nop
/* ... and enable them */
- li t0, CONF_CM_CACHABLE_NONCOHERENT
+ li t0, CONFIG_SYS_MIPS_CACHE_MODE
mtc0 t0, CP0_CONFIG
#endif