From 7185adb48ef1e5b0f05263a7f791de340ddddeb2 Mon Sep 17 00:00:00 2001 From: Daniel Schwierzeck Date: Wed, 27 Jul 2011 13:22:37 +0200 Subject: MIPS: rename INFINEON_EBU_BOOTCFG to CONFIG_SYS_XWAY_EBU_BOOTFG This define is a board-specific config option and should be renamed to follow the U-Boot naming convention. Additionally, add an explaining comment for this option. Signed-off-by: Daniel Schwierzeck Acked-by: Thomas Langer Signed-off-by: Shinya Kuribayashi --- arch/mips/cpu/mips32/start.S | 13 ++++++++++--- 1 file changed, 10 insertions(+), 3 deletions(-) (limited to 'arch') diff --git a/arch/mips/cpu/mips32/start.S b/arch/mips/cpu/mips32/start.S index 5d7467d..e829b02 100644 --- a/arch/mips/cpu/mips32/start.S +++ b/arch/mips/cpu/mips32/start.S @@ -64,9 +64,16 @@ _start: RVECENT(reset,0) # U-boot entry point RVECENT(reset,1) # software reboot -#ifdef CONFIG_INCA_IP - .word INFINEON_EBU_BOOTCFG # EBU init code, fetched during - .word 0x00000000 # booting phase of the flash +#ifdef CONFIG_SYS_XWAY_EBU_BOOTCFG + /* + * Almost all Lantiq XWAY SoC devices have an external bus unit (EBU) to + * access external NOR flashes. If the board boots from NOR flash the + * internal BootROM does a blind read at address 0xB0000010 to read the + * initial configuration for that EBU in order to access the flash + * device with correct parameters. This config option is board-specific. + */ + .word CONFIG_SYS_XWAY_EBU_BOOTCFG + .word 0x00000000 #else RVECENT(romReserved,2) #endif -- cgit v1.1 From ab2a98b11716364bc5a8c43cdfa7fee176cda1d8 Mon Sep 17 00:00:00 2001 From: Daniel Schwierzeck Date: Wed, 27 Jul 2011 13:22:38 +0200 Subject: MIPS: make cache operation mode configurable Currently the cache operation mode is hard-coded to CONF_CM_CACHABLE_NONCOHERENT. This is not appropiate for CPUs or SOCs which operate at a different mode. This patch makes the cache operation mode configurable via board config. Signed-off-by: Daniel Schwierzeck Acked-by: Thomas Langer Signed-off-by: Shinya Kuribayashi --- arch/mips/cpu/mips32/start.S | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/mips/cpu/mips32/start.S b/arch/mips/cpu/mips32/start.S index e829b02..9c1b2f7 100644 --- a/arch/mips/cpu/mips32/start.S +++ b/arch/mips/cpu/mips32/start.S @@ -27,6 +27,10 @@ #include #include +#ifndef CONFIG_SYS_MIPS_CACHE_MODE +#define CONFIG_SYS_MIPS_CACHE_MODE CONF_CM_CACHABLE_NONCOHERENT +#endif + /* * For the moment disable interrupts, mark the kernel mode and * set ST0_KX so that the CPU does not spit fire when using @@ -249,7 +253,7 @@ reset: nop /* ... and enable them */ - li t0, CONF_CM_CACHABLE_NONCOHERENT + li t0, CONFIG_SYS_MIPS_CACHE_MODE mtc0 t0, CP0_CONFIG #endif -- cgit v1.1