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authorTom Rini <trini@ti.com>2013-07-24 09:30:46 -0400
committerTom Rini <trini@ti.com>2013-07-25 08:51:48 -0400
commit230187ce266889ad465b39ded6717805379e7ffe (patch)
treeda91d96b28eba97d7e14ffee800fc1003dac880d /arch
parent8dde4ca90ee12a9dd40f42b80e51107ecd26ebe0 (diff)
parentdb2c86d7d71d1be0ac0fe702493faf9302639235 (diff)
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Merge branch 'master' of git://git.denx.de/u-boot-mips
Conflict over SPDX changes means that one change was effectively dropped as it was fixing typos in a removed hunk of text. Conflicts: arch/mips/cpu/mips64/start.S Signed-off-by: Tom Rini <trini@ti.com>
Diffstat (limited to 'arch')
-rw-r--r--arch/mips/cpu/mips32/cache.S17
-rw-r--r--arch/mips/cpu/mips32/start.S32
-rw-r--r--arch/mips/cpu/mips32/time.c5
-rw-r--r--arch/mips/cpu/mips64/interrupts.c1
-rw-r--r--arch/mips/cpu/mips64/start.S2
-rw-r--r--arch/mips/cpu/xburst/start.S41
-rw-r--r--arch/mips/include/asm/malta.h23
7 files changed, 76 insertions, 45 deletions
diff --git a/arch/mips/cpu/mips32/cache.S b/arch/mips/cpu/mips32/cache.S
index 117fc56..12f656c 100644
--- a/arch/mips/cpu/mips32/cache.S
+++ b/arch/mips/cpu/mips32/cache.S
@@ -18,7 +18,7 @@
#define CONFIG_SYS_MIPS_CACHE_MODE CONF_CM_CACHABLE_NONCOHERENT
#endif
-#define RA t8
+#define RA t9
/*
* 16kB is the maximum size of instruction and data caches on MIPS 4K,
@@ -128,8 +128,7 @@ NESTED(mips_cache_reset, 0, ra)
move RA, ra
li t2, CONFIG_SYS_ICACHE_SIZE
li t3, CONFIG_SYS_DCACHE_SIZE
- li t4, CONFIG_SYS_CACHELINE_SIZE
- move t5, t4
+ li t8, CONFIG_SYS_CACHELINE_SIZE
li v0, MIPS_MAX_CACHE_SIZE
@@ -156,17 +155,17 @@ NESTED(mips_cache_reset, 0, ra)
* Initialize the I-cache first,
*/
move a1, t2
- move a2, t4
- PTR_LA t7, mips_init_icache
- jalr t7
+ move a2, t8
+ PTR_LA v1, mips_init_icache
+ jalr v1
/*
* then initialize D-cache.
*/
move a1, t3
- move a2, t5
- PTR_LA t7, mips_init_dcache
- jalr t7
+ move a2, t8
+ PTR_LA v1, mips_init_dcache
+ jalr v1
jr RA
END(mips_cache_reset)
diff --git a/arch/mips/cpu/mips32/start.S b/arch/mips/cpu/mips32/start.S
index b08a897..70ad198 100644
--- a/arch/mips/cpu/mips32/start.S
+++ b/arch/mips/cpu/mips32/start.S
@@ -41,7 +41,7 @@ _start:
nop
.org 0x10
-#ifdef CONFIG_SYS_XWAY_EBU_BOOTCFG
+#if defined(CONFIG_SYS_XWAY_EBU_BOOTCFG)
/*
* Almost all Lantiq XWAY SoC devices have an external bus unit (EBU) to
* access external NOR flashes. If the board boots from NOR flash the
@@ -51,6 +51,12 @@ _start:
*/
.word CONFIG_SYS_XWAY_EBU_BOOTCFG
.word 0x0
+#elif defined(CONFIG_QEMU_MALTA)
+ /*
+ * Linux expects the Board ID here.
+ */
+ .word 0x00000420 # 0x420 (Malta Board with CoreLV)
+ .word 0x00000000
#endif
.org 0x200
@@ -199,19 +205,19 @@ in_ram:
* generated by GNU ld. Skip these reserved entries from relocation.
*/
lw t3, -4(t0) # t3 <-- num_got_entries
- lw t4, -8(t0) # t4 <-- _GLOBAL_OFFSET_TABLE_
- add t4, s1 # t4 now holds relocated _G_O_T_
- addi t4, t4, 8 # skipping first two entries
+ lw t8, -8(t0) # t8 <-- _GLOBAL_OFFSET_TABLE_
+ add t8, s1 # t8 now holds relocated _G_O_T_
+ addi t8, t8, 8 # skipping first two entries
li t2, 2
1:
- lw t1, 0(t4)
+ lw t1, 0(t8)
beqz t1, 2f
add t1, s1
- sw t1, 0(t4)
+ sw t1, 0(t8)
2:
addi t2, 1
blt t2, t3, 1b
- addi t4, 4
+ addi t8, 4
/* Update dynamic relocations */
lw t1, -16(t0) # t1 <-- __rel_dyn_start
@@ -221,19 +227,19 @@ in_ram:
addi t1, 8
1:
- lw t3, -4(t1) # t3 <-- relocation info
+ lw t8, -4(t1) # t8 <-- relocation info
- sub t3, 3
- bnez t3, 2f # skip non R_MIPS_REL32 entries
+ li t3, 3
+ bne t8, t3, 2f # skip non R_MIPS_REL32 entries
nop
lw t3, -8(t1) # t3 <-- location to fix up in FLASH
- lw t4, 0(t3) # t4 <-- original pointer
- add t4, s1 # t4 <-- adjusted pointer
+ lw t8, 0(t3) # t8 <-- original pointer
+ add t8, s1 # t8 <-- adjusted pointer
add t3, s1 # t3 <-- location to fix up in RAM
- sw t4, 0(t3)
+ sw t8, 0(t3)
2:
blt t1, t2, 1b
diff --git a/arch/mips/cpu/mips32/time.c b/arch/mips/cpu/mips32/time.c
index 9f5cea4..386f45a 100644
--- a/arch/mips/cpu/mips32/time.c
+++ b/arch/mips/cpu/mips32/time.c
@@ -11,7 +11,8 @@
static unsigned long timestamp;
/* how many counter cycles in a jiffy */
-#define CYCLES_PER_JIFFY (CONFIG_SYS_MIPS_TIMER_FREQ + CONFIG_SYS_HZ / 2) / CONFIG_SYS_HZ
+#define CYCLES_PER_JIFFY \
+ (CONFIG_SYS_MIPS_TIMER_FREQ + CONFIG_SYS_HZ / 2) / CONFIG_SYS_HZ
/*
* timer without interrupts
@@ -38,7 +39,7 @@ ulong get_timer(ulong base)
}
write_c0_compare(expirelo);
- return (timestamp - base);
+ return timestamp - base;
}
void __udelay(unsigned long usec)
diff --git a/arch/mips/cpu/mips64/interrupts.c b/arch/mips/cpu/mips64/interrupts.c
index 1a589fc..a7e2ed0 100644
--- a/arch/mips/cpu/mips64/interrupts.c
+++ b/arch/mips/cpu/mips64/interrupts.c
@@ -6,7 +6,6 @@
*/
#include <common.h>
-#include <asm/mipsregs.h>
void enable_interrupts(void)
{
diff --git a/arch/mips/cpu/mips64/start.S b/arch/mips/cpu/mips64/start.S
index 478b8c6..92954e1 100644
--- a/arch/mips/cpu/mips64/start.S
+++ b/arch/mips/cpu/mips64/start.S
@@ -3,7 +3,7 @@
*
* Copyright (c) 2003 Wolfgang Denk <wd@denx.de>
*
- * SPDX-License-Identifier: GPL-2.0+
+ * SPDX-License-Identifier: GPL-2.0+
*/
#include <asm-offsets.h>
diff --git a/arch/mips/cpu/xburst/start.S b/arch/mips/cpu/xburst/start.S
index be14b3d..10dffb4 100644
--- a/arch/mips/cpu/xburst/start.S
+++ b/arch/mips/cpu/xburst/start.S
@@ -47,14 +47,17 @@ _start:
relocate_code:
move sp, a0 # set new stack pointer
+ move s0, a1 # save gd in s0
+ move s2, a2 # save destination address in s2
+
li t0, CONFIG_SYS_MONITOR_BASE
- sub t6, a2, t0 # t6 <-- relocation offset
+ sub s1, s2, t0 # s1 <-- relocation offset
la t3, in_ram
lw t2, -12(t3) # t2 <-- __image_copy_end
move t1, a2
- add gp, t6 # adjust gp
+ add gp, s1 # adjust gp
/*
* t0 = source address
@@ -96,7 +99,7 @@ relocate_code:
nop
/* Jump to where we've relocated ourselves */
- addi t0, a2, in_ram - _start
+ addi t0, s2, in_ram - _start
jr t0
nop
@@ -114,19 +117,19 @@ in_ram:
* generated by GNU ld. Skip these reserved entries from relocation.
*/
lw t3, -4(t0) # t3 <-- num_got_entries
- lw t4, -8(t0) # t4 <-- _GLOBAL_OFFSET_TABLE_
- add t4, t6 # t4 now holds relocated _G_O_T_
- addi t4, t4, 8 # skipping first two entries
+ lw t8, -8(t0) # t8 <-- _GLOBAL_OFFSET_TABLE_
+ add t8, s1 # t8 now holds relocated _G_O_T_
+ addi t8, t8, 8 # skipping first two entries
li t2, 2
1:
- lw t1, 0(t4)
+ lw t1, 0(t8)
beqz t1, 2f
- add t1, t6
- sw t1, 0(t4)
+ add t1, s1
+ sw t1, 0(t8)
2:
addi t2, 1
blt t2, t3, 1b
- addi t4, 4
+ addi t8, 4
/* Update dynamic relocations */
lw t1, -16(t0) # t1 <-- __rel_dyn_start
@@ -136,19 +139,19 @@ in_ram:
addi t1, 8
1:
- lw t3, -4(t1) # t3 <-- relocation info
+ lw t8, -4(t1) # t8 <-- relocation info
- sub t3, 3
- bnez t3, 2f # skip non R_MIPS_REL32 entries
+ li t3, 3
+ bne t8, t3, 2f # skip non R_MIPS_REL32 entries
nop
lw t3, -8(t1) # t3 <-- location to fix up in FLASH
- lw t4, 0(t3) # t4 <-- original pointer
- add t4, t6 # t4 <-- adjusted pointer
+ lw t8, 0(t3) # t8 <-- original pointer
+ add t8, s1 # t8 <-- adjusted pointer
- add t3, t6 # t3 <-- location to fix up in RAM
- sw t4, 0(t3)
+ add t3, s1 # t3 <-- location to fix up in RAM
+ sw t8, 0(t3)
2:
blt t1, t2, 1b
@@ -168,9 +171,9 @@ in_ram:
blt t1, t2, 1b
addi t1, 4
- move a0, a1 # a0 <-- gd
+ move a0, s0 # a0 <-- gd
la t9, board_init_r
jr t9
- move a1, a2
+ move a1, s2
.end relocate_code
diff --git a/arch/mips/include/asm/malta.h b/arch/mips/include/asm/malta.h
new file mode 100644
index 0000000..d4d44a2
--- /dev/null
+++ b/arch/mips/include/asm/malta.h
@@ -0,0 +1,23 @@
+/*
+ * Copyright (C) 2013 Gabor Juhos <juhosg@openwrt.org>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ */
+
+#ifndef _MIPS_ASM_MALTA_H
+#define _MIPS_ASM_MALTA_H
+
+#define MALTA_IO_PORT_BASE 0x18000000
+
+#define MALTA_UART_BASE (MALTA_IO_PORT_BASE + 0x3f8)
+
+#define MALTA_GT_BASE 0x1be00000
+
+#define MALTA_RESET_BASE 0x1f000500
+#define GORESET 0x42
+
+#define MALTA_FLASH_BASE 0x1fc00000
+
+#endif /* _MIPS_ASM_MALTA_H */