From 518d4385375d6f9b8da2e395ac85482809f137d1 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Wed, 24 Jul 2013 09:50:52 -0400 Subject: MIPS: mips64: fix typos in copyright text of start.S Signed-off-by: Gabor Juhos Cc: Daniel Schwierzeck Conflicts: arch/mips/cpu/mips64/start.S Signed-off-by: Tom Rini --- arch/mips/cpu/mips64/start.S | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/mips/cpu/mips64/start.S b/arch/mips/cpu/mips64/start.S index 478b8c6..92954e1 100644 --- a/arch/mips/cpu/mips64/start.S +++ b/arch/mips/cpu/mips64/start.S @@ -3,7 +3,7 @@ * * Copyright (c) 2003 Wolfgang Denk * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #include -- cgit v1.1 From 843a76b66be70a28a55f295fa72faa74dde9e02b Mon Sep 17 00:00:00 2001 From: Gabor Juhos Date: Wed, 22 May 2013 03:57:46 +0000 Subject: MIPS: start.S: emulate REVISION register for qemu-malta On the origial Malta boards the REVISION register is accessible at the 0x1fc00010 address. The contents of this register gives information about the revision of the Malta and Core Boards. This register is used by the Linux kernel to identify the actual board it is running on. However the register is not emulated properly by Qemu, so put a hardcoded value into the flash to make Linux work. Signed-off-by: Gabor Juhos Cc: Daniel Schwierzeck --- arch/mips/cpu/mips32/start.S | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/mips/cpu/mips32/start.S b/arch/mips/cpu/mips32/start.S index b08a897..2f1e486 100644 --- a/arch/mips/cpu/mips32/start.S +++ b/arch/mips/cpu/mips32/start.S @@ -41,7 +41,7 @@ _start: nop .org 0x10 -#ifdef CONFIG_SYS_XWAY_EBU_BOOTCFG +#if defined(CONFIG_SYS_XWAY_EBU_BOOTCFG) /* * Almost all Lantiq XWAY SoC devices have an external bus unit (EBU) to * access external NOR flashes. If the board boots from NOR flash the @@ -51,6 +51,12 @@ _start: */ .word CONFIG_SYS_XWAY_EBU_BOOTCFG .word 0x0 +#elif defined(CONFIG_QEMU_MALTA) + /* + * Linux expects the Board ID here. + */ + .word 0x00000420 # 0x420 (Malta Board with CoreLV) + .word 0x00000000 #endif .org 0x200 -- cgit v1.1 From 5a4dcfac1e05f7c025a465d3372a1c1425004c2b Mon Sep 17 00:00:00 2001 From: Gabor Juhos Date: Wed, 22 May 2013 03:57:37 +0000 Subject: MIPS: qemu-malta: add support for emulated MIPS Malta board Add minimal support for the MIPS Malta CoreLV board emulated by Qemu. The only supported peripherial is the UART. This is enough to boot U-Boot to the command prompt both in little and big endian mode. Signed-off-by: Gabor Juhos Cc: Daniel Schwierzeck --- arch/mips/include/asm/malta.h | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) create mode 100644 arch/mips/include/asm/malta.h (limited to 'arch') diff --git a/arch/mips/include/asm/malta.h b/arch/mips/include/asm/malta.h new file mode 100644 index 0000000..b215164 --- /dev/null +++ b/arch/mips/include/asm/malta.h @@ -0,0 +1,16 @@ +/* + * Copyright (C) 2013 Gabor Juhos + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#ifndef _MIPS_ASM_MALTA_H +#define _MIPS_ASM_MALTA_H + +#define MALTA_IO_PORT_BASE 0x10000000 + +#define MALTA_UART_BASE (MALTA_IO_PORT_BASE + 0x3f8) + +#endif /* _MIPS_ASM_MALTA_H */ -- cgit v1.1 From 015643152aee4c333e3f95d153347f50b7e92ea7 Mon Sep 17 00:00:00 2001 From: Gabor Juhos Date: Wed, 22 May 2013 03:57:38 +0000 Subject: MIPS: qemu-malta: add reset support The MIPS Malta board has a SOFTRES register. Writing a magic value into that register initiates a board reset. Use this feature to implement reset support. Signed-off-by: Gabor Juhos Cc: Daniel Schwierzeck --- arch/mips/include/asm/malta.h | 3 +++ 1 file changed, 3 insertions(+) (limited to 'arch') diff --git a/arch/mips/include/asm/malta.h b/arch/mips/include/asm/malta.h index b215164..f2bbf0f 100644 --- a/arch/mips/include/asm/malta.h +++ b/arch/mips/include/asm/malta.h @@ -13,4 +13,7 @@ #define MALTA_UART_BASE (MALTA_IO_PORT_BASE + 0x3f8) +#define MALTA_RESET_BASE 0x1f000500 +#define GORESET 0x42 + #endif /* _MIPS_ASM_MALTA_H */ -- cgit v1.1 From 52caee0f36d86c660b7e139d29db01eac04274bd Mon Sep 17 00:00:00 2001 From: Gabor Juhos Date: Wed, 22 May 2013 03:57:39 +0000 Subject: MIPS: qemu-malta: enable flash support Signed-off-by: Gabor Juhos Cc: Daniel Schwierzeck --- arch/mips/include/asm/malta.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch') diff --git a/arch/mips/include/asm/malta.h b/arch/mips/include/asm/malta.h index f2bbf0f..ab951e6 100644 --- a/arch/mips/include/asm/malta.h +++ b/arch/mips/include/asm/malta.h @@ -16,4 +16,6 @@ #define MALTA_RESET_BASE 0x1f000500 #define GORESET 0x42 +#define MALTA_FLASH_BASE 0x1fc00000 + #endif /* _MIPS_ASM_MALTA_H */ -- cgit v1.1 From ac12984de8e2239a19c054ffcc615ad4a2e57cc4 Mon Sep 17 00:00:00 2001 From: Gabor Juhos Date: Wed, 22 May 2013 03:57:41 +0000 Subject: MIPS: qemu-malta: setup GT64120 registers as done by YAMON Move the GT64120 register base to 0x1be00000 and setup PCI BAR registers as done by the original YAMON bootloader. This is needed for running Linux kernel. Signed-off-by: Gabor Juhos Cc: Daniel Schwierzeck --- arch/mips/include/asm/malta.h | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/mips/include/asm/malta.h b/arch/mips/include/asm/malta.h index ab951e6..d4d44a2 100644 --- a/arch/mips/include/asm/malta.h +++ b/arch/mips/include/asm/malta.h @@ -9,10 +9,12 @@ #ifndef _MIPS_ASM_MALTA_H #define _MIPS_ASM_MALTA_H -#define MALTA_IO_PORT_BASE 0x10000000 +#define MALTA_IO_PORT_BASE 0x18000000 #define MALTA_UART_BASE (MALTA_IO_PORT_BASE + 0x3f8) +#define MALTA_GT_BASE 0x1be00000 + #define MALTA_RESET_BASE 0x1f000500 #define GORESET 0x42 -- cgit v1.1 From c3e4901fc66f62c6ef54b849b0f29bde1d5c0b70 Mon Sep 17 00:00:00 2001 From: Gabor Juhos Date: Wed, 12 Jun 2013 18:02:43 +0200 Subject: MIPS: mips32/time.c: fix checkpatch errors/warnings Checking mips32/time.c with checkpatch.pl shows this: arch/mips/cpu/mips32/time.c:30: WARNING: line over 80 characters arch/mips/cpu/mips32/time.c:57: ERROR: return is not a function, parentheses are not required total: 1 errors, 1 warnings, 0 checks, 85 lines checked Fix the code to make checkpatch.pl happy. Signed-off-by: Gabor Juhos Cc: Daniel Schwierzeck --- arch/mips/cpu/mips32/time.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) (limited to 'arch') diff --git a/arch/mips/cpu/mips32/time.c b/arch/mips/cpu/mips32/time.c index 9f5cea4..386f45a 100644 --- a/arch/mips/cpu/mips32/time.c +++ b/arch/mips/cpu/mips32/time.c @@ -11,7 +11,8 @@ static unsigned long timestamp; /* how many counter cycles in a jiffy */ -#define CYCLES_PER_JIFFY (CONFIG_SYS_MIPS_TIMER_FREQ + CONFIG_SYS_HZ / 2) / CONFIG_SYS_HZ +#define CYCLES_PER_JIFFY \ + (CONFIG_SYS_MIPS_TIMER_FREQ + CONFIG_SYS_HZ / 2) / CONFIG_SYS_HZ /* * timer without interrupts @@ -38,7 +39,7 @@ ulong get_timer(ulong base) } write_c0_compare(expirelo); - return (timestamp - base); + return timestamp - base; } void __udelay(unsigned long usec) -- cgit v1.1 From b1591ec2461646556782dc7c6f9cbfada39302b0 Mon Sep 17 00:00:00 2001 From: Gabor Juhos Date: Wed, 12 Jun 2013 18:02:44 +0200 Subject: MIPS: mips64/interrupt.c: remove superfluous include Nothing is used from asm/mipsregs.h. Signed-off-by: Gabor Juhos Cc: Daniel Schwierzeck --- arch/mips/cpu/mips64/interrupts.c | 1 - 1 file changed, 1 deletion(-) (limited to 'arch') diff --git a/arch/mips/cpu/mips64/interrupts.c b/arch/mips/cpu/mips64/interrupts.c index 1a589fc..a7e2ed0 100644 --- a/arch/mips/cpu/mips64/interrupts.c +++ b/arch/mips/cpu/mips64/interrupts.c @@ -6,7 +6,6 @@ */ #include -#include void enable_interrupts(void) { -- cgit v1.1 From da84f33b046fe99c5fbb6f7d8f8b03c7333b260d Mon Sep 17 00:00:00 2001 From: Gabor Juhos Date: Wed, 12 Jun 2013 18:02:46 +0200 Subject: MIPS: mips32/cache.S: remove superfluous register assignment The t4 register already holds the cache line size, and the value of the register is not changed in mips_init_icache. Get the cache line size value from t4 for mips_init_dcache as well and remove the superfluous assignment of t5 register. Signed-off-by: Gabor Juhos --- arch/mips/cpu/mips32/cache.S | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) (limited to 'arch') diff --git a/arch/mips/cpu/mips32/cache.S b/arch/mips/cpu/mips32/cache.S index 117fc56..40bb46e 100644 --- a/arch/mips/cpu/mips32/cache.S +++ b/arch/mips/cpu/mips32/cache.S @@ -129,7 +129,6 @@ NESTED(mips_cache_reset, 0, ra) li t2, CONFIG_SYS_ICACHE_SIZE li t3, CONFIG_SYS_DCACHE_SIZE li t4, CONFIG_SYS_CACHELINE_SIZE - move t5, t4 li v0, MIPS_MAX_CACHE_SIZE @@ -164,7 +163,7 @@ NESTED(mips_cache_reset, 0, ra) * then initialize D-cache. */ move a1, t3 - move a2, t5 + move a2, t4 PTR_LA t7, mips_init_dcache jalr t7 -- cgit v1.1 From 680cb2dc3a7ba1a9a5e8ca919d980e99906a767b Mon Sep 17 00:00:00 2001 From: Gabor Juhos Date: Thu, 13 Jun 2013 12:59:27 +0200 Subject: MIPS: mips32/start.S: use t8 register for dynamic relocation Synchronize the code with mips64/start.S, in order to allow further unifications. Signed-off-by: Gabor Juhos Cc: Daniel Schwierzeck --- arch/mips/cpu/mips32/start.S | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) (limited to 'arch') diff --git a/arch/mips/cpu/mips32/start.S b/arch/mips/cpu/mips32/start.S index 2f1e486..f5ebe79 100644 --- a/arch/mips/cpu/mips32/start.S +++ b/arch/mips/cpu/mips32/start.S @@ -205,19 +205,19 @@ in_ram: * generated by GNU ld. Skip these reserved entries from relocation. */ lw t3, -4(t0) # t3 <-- num_got_entries - lw t4, -8(t0) # t4 <-- _GLOBAL_OFFSET_TABLE_ - add t4, s1 # t4 now holds relocated _G_O_T_ - addi t4, t4, 8 # skipping first two entries + lw t8, -8(t0) # t8 <-- _GLOBAL_OFFSET_TABLE_ + add t8, s1 # t8 now holds relocated _G_O_T_ + addi t8, t8, 8 # skipping first two entries li t2, 2 1: - lw t1, 0(t4) + lw t1, 0(t8) beqz t1, 2f add t1, s1 - sw t1, 0(t4) + sw t1, 0(t8) 2: addi t2, 1 blt t2, t3, 1b - addi t4, 4 + addi t8, 4 /* Update dynamic relocations */ lw t1, -16(t0) # t1 <-- __rel_dyn_start @@ -235,11 +235,11 @@ in_ram: lw t3, -8(t1) # t3 <-- location to fix up in FLASH - lw t4, 0(t3) # t4 <-- original pointer - add t4, s1 # t4 <-- adjusted pointer + lw t8, 0(t3) # t8 <-- original pointer + add t8, s1 # t8 <-- adjusted pointer add t3, s1 # t3 <-- location to fix up in RAM - sw t4, 0(t3) + sw t8, 0(t3) 2: blt t1, t2, 1b -- cgit v1.1 From 691995f9ab672be1141ca8acfa7ff32508084782 Mon Sep 17 00:00:00 2001 From: Gabor Juhos Date: Thu, 13 Jun 2013 12:59:28 +0200 Subject: MIPS: mips32/start.S: rework relocation info check Make it similar to the code in mips64/start.S, in order to allow further unifications. Signed-off-by: Gabor Juhos Cc: Daniel Schwierzeck --- arch/mips/cpu/mips32/start.S | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'arch') diff --git a/arch/mips/cpu/mips32/start.S b/arch/mips/cpu/mips32/start.S index f5ebe79..70ad198 100644 --- a/arch/mips/cpu/mips32/start.S +++ b/arch/mips/cpu/mips32/start.S @@ -227,10 +227,10 @@ in_ram: addi t1, 8 1: - lw t3, -4(t1) # t3 <-- relocation info + lw t8, -4(t1) # t8 <-- relocation info - sub t3, 3 - bnez t3, 2f # skip non R_MIPS_REL32 entries + li t3, 3 + bne t8, t3, 2f # skip non R_MIPS_REL32 entries nop lw t3, -8(t1) # t3 <-- location to fix up in FLASH -- cgit v1.1 From 9a28e0d177d7714baccf282071d99f70e087a4e4 Mon Sep 17 00:00:00 2001 From: Gabor Juhos Date: Thu, 13 Jun 2013 12:59:29 +0200 Subject: MIPS: xburst/start.S: save relocation address in s2 register Synchronize the code with mips{32,64}/start.S, in order to allow further unifications. Signed-off-by: Gabor Juhos Cc: Daniel Schwierzeck --- arch/mips/cpu/xburst/start.S | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) (limited to 'arch') diff --git a/arch/mips/cpu/xburst/start.S b/arch/mips/cpu/xburst/start.S index be14b3d..052e25e 100644 --- a/arch/mips/cpu/xburst/start.S +++ b/arch/mips/cpu/xburst/start.S @@ -47,8 +47,10 @@ _start: relocate_code: move sp, a0 # set new stack pointer + move s2, a2 # save destination address in s2 + li t0, CONFIG_SYS_MONITOR_BASE - sub t6, a2, t0 # t6 <-- relocation offset + sub t6, s2, t0 # t6 <-- relocation offset la t3, in_ram lw t2, -12(t3) # t2 <-- __image_copy_end @@ -96,7 +98,7 @@ relocate_code: nop /* Jump to where we've relocated ourselves */ - addi t0, a2, in_ram - _start + addi t0, s2, in_ram - _start jr t0 nop @@ -171,6 +173,6 @@ in_ram: move a0, a1 # a0 <-- gd la t9, board_init_r jr t9 - move a1, a2 + move a1, s2 .end relocate_code -- cgit v1.1 From ba9cf07122ce7ab3a10ab2873deb890bf2c72bd9 Mon Sep 17 00:00:00 2001 From: Gabor Juhos Date: Thu, 13 Jun 2013 12:59:30 +0200 Subject: MIPS: xburst/start.S: save relocation offset in s1 register Synchronize the code with mips{32,64}/start.S, in order to allow further unifications. Signed-off-by: Gabor Juhos Cc: Daniel Schwierzeck --- arch/mips/cpu/xburst/start.S | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) (limited to 'arch') diff --git a/arch/mips/cpu/xburst/start.S b/arch/mips/cpu/xburst/start.S index 052e25e..2dfd27e 100644 --- a/arch/mips/cpu/xburst/start.S +++ b/arch/mips/cpu/xburst/start.S @@ -50,13 +50,13 @@ relocate_code: move s2, a2 # save destination address in s2 li t0, CONFIG_SYS_MONITOR_BASE - sub t6, s2, t0 # t6 <-- relocation offset + sub s1, s2, t0 # s1 <-- relocation offset la t3, in_ram lw t2, -12(t3) # t2 <-- __image_copy_end move t1, a2 - add gp, t6 # adjust gp + add gp, s1 # adjust gp /* * t0 = source address @@ -117,13 +117,13 @@ in_ram: */ lw t3, -4(t0) # t3 <-- num_got_entries lw t4, -8(t0) # t4 <-- _GLOBAL_OFFSET_TABLE_ - add t4, t6 # t4 now holds relocated _G_O_T_ + add t4, s1 # t4 now holds relocated _G_O_T_ addi t4, t4, 8 # skipping first two entries li t2, 2 1: lw t1, 0(t4) beqz t1, 2f - add t1, t6 + add t1, s1 sw t1, 0(t4) 2: addi t2, 1 @@ -147,9 +147,9 @@ in_ram: lw t3, -8(t1) # t3 <-- location to fix up in FLASH lw t4, 0(t3) # t4 <-- original pointer - add t4, t6 # t4 <-- adjusted pointer + add t4, s1 # t4 <-- adjusted pointer - add t3, t6 # t3 <-- location to fix up in RAM + add t3, s1 # t3 <-- location to fix up in RAM sw t4, 0(t3) 2: -- cgit v1.1 From f01d6935350d1487bfc26d06f0f6888e1ab47236 Mon Sep 17 00:00:00 2001 From: Gabor Juhos Date: Thu, 13 Jun 2013 12:59:31 +0200 Subject: MIPS: xburst/start.S: save gd in s0 register Synchronize the code with mips{32,64}/start.S, in order to allow further unifications. Signed-off-by: Gabor Juhos Cc: Daniel Schwierzeck --- arch/mips/cpu/xburst/start.S | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/mips/cpu/xburst/start.S b/arch/mips/cpu/xburst/start.S index 2dfd27e..6adabdc 100644 --- a/arch/mips/cpu/xburst/start.S +++ b/arch/mips/cpu/xburst/start.S @@ -47,6 +47,7 @@ _start: relocate_code: move sp, a0 # set new stack pointer + move s0, a1 # save gd in s0 move s2, a2 # save destination address in s2 li t0, CONFIG_SYS_MONITOR_BASE @@ -170,7 +171,7 @@ in_ram: blt t1, t2, 1b addi t1, 4 - move a0, a1 # a0 <-- gd + move a0, s0 # a0 <-- gd la t9, board_init_r jr t9 move a1, s2 -- cgit v1.1 From e5c868a2089d5aad3c91e008dc978c78012f1fa1 Mon Sep 17 00:00:00 2001 From: Gabor Juhos Date: Thu, 13 Jun 2013 12:59:32 +0200 Subject: MIPS: xburst/start.S: use t8 register for dynamic relocation Synchronize the code with mips{32,64}/start.S, in order to allow further unifications. Signed-off-by: Gabor Juhos Cc: Daniel Schwierzeck --- arch/mips/cpu/xburst/start.S | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) (limited to 'arch') diff --git a/arch/mips/cpu/xburst/start.S b/arch/mips/cpu/xburst/start.S index 6adabdc..e5ff4e0 100644 --- a/arch/mips/cpu/xburst/start.S +++ b/arch/mips/cpu/xburst/start.S @@ -117,19 +117,19 @@ in_ram: * generated by GNU ld. Skip these reserved entries from relocation. */ lw t3, -4(t0) # t3 <-- num_got_entries - lw t4, -8(t0) # t4 <-- _GLOBAL_OFFSET_TABLE_ - add t4, s1 # t4 now holds relocated _G_O_T_ - addi t4, t4, 8 # skipping first two entries + lw t8, -8(t0) # t8 <-- _GLOBAL_OFFSET_TABLE_ + add t8, s1 # t8 now holds relocated _G_O_T_ + addi t8, t8, 8 # skipping first two entries li t2, 2 1: - lw t1, 0(t4) + lw t1, 0(t8) beqz t1, 2f add t1, s1 - sw t1, 0(t4) + sw t1, 0(t8) 2: addi t2, 1 blt t2, t3, 1b - addi t4, 4 + addi t8, 4 /* Update dynamic relocations */ lw t1, -16(t0) # t1 <-- __rel_dyn_start @@ -147,11 +147,11 @@ in_ram: lw t3, -8(t1) # t3 <-- location to fix up in FLASH - lw t4, 0(t3) # t4 <-- original pointer - add t4, s1 # t4 <-- adjusted pointer + lw t8, 0(t3) # t8 <-- original pointer + add t8, s1 # t8 <-- adjusted pointer add t3, s1 # t3 <-- location to fix up in RAM - sw t4, 0(t3) + sw t8, 0(t3) 2: blt t1, t2, 1b -- cgit v1.1 From d707e5b713e1188556027d835a542d1fc888179d Mon Sep 17 00:00:00 2001 From: Gabor Juhos Date: Fri, 14 Jun 2013 14:47:10 +0200 Subject: MIPS: xburst/start.S: rework relocation info check Make it similar to the code in mips{32,64}/start.S, in order to allow further unifications. Signed-off-by: Gabor Juhos Cc: Daniel Schwierzeck --- arch/mips/cpu/xburst/start.S | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'arch') diff --git a/arch/mips/cpu/xburst/start.S b/arch/mips/cpu/xburst/start.S index e5ff4e0..10dffb4 100644 --- a/arch/mips/cpu/xburst/start.S +++ b/arch/mips/cpu/xburst/start.S @@ -139,10 +139,10 @@ in_ram: addi t1, 8 1: - lw t3, -4(t1) # t3 <-- relocation info + lw t8, -4(t1) # t8 <-- relocation info - sub t3, 3 - bnez t3, 2f # skip non R_MIPS_REL32 entries + li t3, 3 + bne t8, t3, 2f # skip non R_MIPS_REL32 entries nop lw t3, -8(t1) # t3 <-- location to fix up in FLASH -- cgit v1.1 From c325916563ac67ec5f86748060c2909a9b960bee Mon Sep 17 00:00:00 2001 From: Gabor Juhos Date: Thu, 13 Jun 2013 12:59:34 +0200 Subject: MIPS: mips32/cache.S: save return address in t9 register Synchronize the code with mips64/cache.S, in order to allow further unifications. Signed-off-by: Gabor Juhos Cc: Daniel Schwierzeck --- arch/mips/cpu/mips32/cache.S | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/mips/cpu/mips32/cache.S b/arch/mips/cpu/mips32/cache.S index 40bb46e..fc13d3f 100644 --- a/arch/mips/cpu/mips32/cache.S +++ b/arch/mips/cpu/mips32/cache.S @@ -18,7 +18,7 @@ #define CONFIG_SYS_MIPS_CACHE_MODE CONF_CM_CACHABLE_NONCOHERENT #endif -#define RA t8 +#define RA t9 /* * 16kB is the maximum size of instruction and data caches on MIPS 4K, -- cgit v1.1 From ee8b1e29597bcf18bfebd6fd8eccc8e245046352 Mon Sep 17 00:00:00 2001 From: Gabor Juhos Date: Thu, 13 Jun 2013 12:59:35 +0200 Subject: MIPS: mips32/cache.S: store cache line size in t8 register Synchronize the code with mips64/cache.S, in order to allow further unifications. Signed-off-by: Gabor Juhos Cc: Daniel Schwierzeck --- arch/mips/cpu/mips32/cache.S | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'arch') diff --git a/arch/mips/cpu/mips32/cache.S b/arch/mips/cpu/mips32/cache.S index fc13d3f..d3f156e 100644 --- a/arch/mips/cpu/mips32/cache.S +++ b/arch/mips/cpu/mips32/cache.S @@ -128,7 +128,7 @@ NESTED(mips_cache_reset, 0, ra) move RA, ra li t2, CONFIG_SYS_ICACHE_SIZE li t3, CONFIG_SYS_DCACHE_SIZE - li t4, CONFIG_SYS_CACHELINE_SIZE + li t8, CONFIG_SYS_CACHELINE_SIZE li v0, MIPS_MAX_CACHE_SIZE @@ -155,7 +155,7 @@ NESTED(mips_cache_reset, 0, ra) * Initialize the I-cache first, */ move a1, t2 - move a2, t4 + move a2, t8 PTR_LA t7, mips_init_icache jalr t7 @@ -163,7 +163,7 @@ NESTED(mips_cache_reset, 0, ra) * then initialize D-cache. */ move a1, t3 - move a2, t4 + move a2, t8 PTR_LA t7, mips_init_dcache jalr t7 -- cgit v1.1 From db2c86d7d71d1be0ac0fe702493faf9302639235 Mon Sep 17 00:00:00 2001 From: Gabor Juhos Date: Thu, 13 Jun 2013 12:59:36 +0200 Subject: MIPS: mips32/cache.S: use v1 register for indirect function calls Synchronize the code with mips64/cache.S, in order to allow further unifications. Signed-off-by: Gabor Juhos Cc: Daniel Schwierzeck --- arch/mips/cpu/mips32/cache.S | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'arch') diff --git a/arch/mips/cpu/mips32/cache.S b/arch/mips/cpu/mips32/cache.S index d3f156e..12f656c 100644 --- a/arch/mips/cpu/mips32/cache.S +++ b/arch/mips/cpu/mips32/cache.S @@ -156,16 +156,16 @@ NESTED(mips_cache_reset, 0, ra) */ move a1, t2 move a2, t8 - PTR_LA t7, mips_init_icache - jalr t7 + PTR_LA v1, mips_init_icache + jalr v1 /* * then initialize D-cache. */ move a1, t3 move a2, t8 - PTR_LA t7, mips_init_dcache - jalr t7 + PTR_LA v1, mips_init_dcache + jalr v1 jr RA END(mips_cache_reset) -- cgit v1.1