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| author | Aneesh V <aneesh@ti.com> | 2011-08-11 04:35:44 +0000 |
|---|---|---|
| committer | Albert ARIBAUD <albert.u.boot@aribaud.net> | 2011-09-04 11:36:16 +0200 |
| commit | 882f80b993f3719cce5bfa7f1bca9b1b23062b5f (patch) | |
| tree | ba83eab86729a1871261d10512178ccc1d2c9a65 /arch | |
| parent | 13d4f9bd7477b3b409f3e267b3b3d6fed5bd3e30 (diff) | |
| download | u-boot-imx-882f80b993f3719cce5bfa7f1bca9b1b23062b5f.zip u-boot-imx-882f80b993f3719cce5bfa7f1bca9b1b23062b5f.tar.gz u-boot-imx-882f80b993f3719cce5bfa7f1bca9b1b23062b5f.tar.bz2 | |
armv7: stronger barrier for cache-maintenance operations
set-way operations need a DSB after them to ensure the
operation is complete. DMB may not be enough. Use DSB
after all operations instead of DMB.
Signed-off-by: Aneesh V <aneesh@ti.com>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/cpu/armv7/cache_v7.c | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/arch/arm/cpu/armv7/cache_v7.c b/arch/arm/cpu/armv7/cache_v7.c index 3e1e1bf..665f025 100644 --- a/arch/arm/cpu/armv7/cache_v7.c +++ b/arch/arm/cpu/armv7/cache_v7.c @@ -81,8 +81,8 @@ static void v7_inval_dcache_level_setway(u32 level, u32 num_sets, : : "r" (setway)); } } - /* DMB to make sure the operation is complete */ - CP15DMB; + /* DSB to make sure the operation is complete */ + CP15DSB; } static void v7_clean_inval_dcache_level_setway(u32 level, u32 num_sets, @@ -108,8 +108,8 @@ static void v7_clean_inval_dcache_level_setway(u32 level, u32 num_sets, : : "r" (setway)); } } - /* DMB to make sure the operation is complete */ - CP15DMB; + /* DSB to make sure the operation is complete */ + CP15DSB; } static void v7_maint_dcache_level_setway(u32 level, u32 operation) @@ -227,8 +227,8 @@ static void v7_dcache_maint_range(u32 start, u32 stop, u32 range_op) break; } - /* DMB to make sure the operation is complete */ - CP15DMB; + /* DSB to make sure the operation is complete */ + CP15DSB; } /* Invalidate TLB */ |