From 882f80b993f3719cce5bfa7f1bca9b1b23062b5f Mon Sep 17 00:00:00 2001 From: Aneesh V Date: Thu, 11 Aug 2011 04:35:44 +0000 Subject: armv7: stronger barrier for cache-maintenance operations set-way operations need a DSB after them to ensure the operation is complete. DMB may not be enough. Use DSB after all operations instead of DMB. Signed-off-by: Aneesh V --- arch/arm/cpu/armv7/cache_v7.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) (limited to 'arch') diff --git a/arch/arm/cpu/armv7/cache_v7.c b/arch/arm/cpu/armv7/cache_v7.c index 3e1e1bf..665f025 100644 --- a/arch/arm/cpu/armv7/cache_v7.c +++ b/arch/arm/cpu/armv7/cache_v7.c @@ -81,8 +81,8 @@ static void v7_inval_dcache_level_setway(u32 level, u32 num_sets, : : "r" (setway)); } } - /* DMB to make sure the operation is complete */ - CP15DMB; + /* DSB to make sure the operation is complete */ + CP15DSB; } static void v7_clean_inval_dcache_level_setway(u32 level, u32 num_sets, @@ -108,8 +108,8 @@ static void v7_clean_inval_dcache_level_setway(u32 level, u32 num_sets, : : "r" (setway)); } } - /* DMB to make sure the operation is complete */ - CP15DMB; + /* DSB to make sure the operation is complete */ + CP15DSB; } static void v7_maint_dcache_level_setway(u32 level, u32 operation) @@ -227,8 +227,8 @@ static void v7_dcache_maint_range(u32 start, u32 stop, u32 range_op) break; } - /* DMB to make sure the operation is complete */ - CP15DMB; + /* DSB to make sure the operation is complete */ + CP15DSB; } /* Invalidate TLB */ -- cgit v1.1