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author | Chris Zankel <chris@zankel.net> | 2016-08-10 18:36:44 +0300 |
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committer | Tom Rini <trini@konsulko.com> | 2016-08-15 18:46:38 -0400 |
commit | c978b52410016b0ab5a213f235596340af8d45f7 (patch) | |
tree | b01e9a8ea9a92fe962a545974339677b87dcc1ba /arch/xtensa/include/asm/system.h | |
parent | de5e5cea022ab44006ff1edf45a39f0943fb9dff (diff) | |
download | u-boot-imx-c978b52410016b0ab5a213f235596340af8d45f7.zip u-boot-imx-c978b52410016b0ab5a213f235596340af8d45f7.tar.gz u-boot-imx-c978b52410016b0ab5a213f235596340af8d45f7.tar.bz2 |
xtensa: add support for the xtensa processor architecture [2/2]
The Xtensa processor architecture is a configurable, extensible,
and synthesizable 32-bit RISC processor core provided by Tensilica, inc.
This is the second part of the basic architecture port, adding the
'arch/xtensa' directory and a readme file.
Signed-off-by: Chris Zankel <chris@zankel.net>
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
Diffstat (limited to 'arch/xtensa/include/asm/system.h')
-rw-r--r-- | arch/xtensa/include/asm/system.h | 27 |
1 files changed, 27 insertions, 0 deletions
diff --git a/arch/xtensa/include/asm/system.h b/arch/xtensa/include/asm/system.h new file mode 100644 index 0000000..5b71008 --- /dev/null +++ b/arch/xtensa/include/asm/system.h @@ -0,0 +1,27 @@ +/* + * Copyright (C) 2016 Cadence Design Systems Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _XTENSA_SYSTEM_H +#define _XTENSA_SYSTEM_H + +#include <asm/arch/core.h> + +#if XCHAL_HAVE_INTERRUPTS +#define local_irq_save(flags) \ + __asm__ __volatile__ ("rsil %0, %1" \ + : "=a"(flags) \ + : "I"(XCHAL_EXCM_LEVEL) \ + : "memory") +#define local_irq_restore(flags) \ + __asm__ __volatile__ ("wsr %0, ps\n\t" \ + "rsync" \ + :: "a"(flags) : "memory") +#else +#define local_irq_save(flags) ((void)(flags)) +#define local_irq_restore(flags) ((void)(flags)) +#endif + +#endif |