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| author | Bin Meng <bmeng.cn@gmail.com> | 2015-12-11 02:55:52 -0800 |
|---|---|---|
| committer | Bin Meng <bmeng.cn@gmail.com> | 2016-01-13 12:20:15 +0800 |
| commit | 87968de31d4771947fb7e88d451b0e516178ebf1 (patch) | |
| tree | 94d1638064ee4f83723bb1344536fbcbe374ea9a /arch/x86/include/asm/arch-ivybridge | |
| parent | 59fb7fbd49b5507204501bd5dce91d6f5ac29814 (diff) | |
| download | u-boot-imx-87968de31d4771947fb7e88d451b0e516178ebf1.zip u-boot-imx-87968de31d4771947fb7e88d451b0e516178ebf1.tar.gz u-boot-imx-87968de31d4771947fb7e88d451b0e516178ebf1.tar.bz2 | |
x86: ivybridge: Add macros for LPC decode ranges
Add several macros for LPC decode registers on PCH.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Diffstat (limited to 'arch/x86/include/asm/arch-ivybridge')
| -rw-r--r-- | arch/x86/include/asm/arch-ivybridge/pch.h | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/arch/x86/include/asm/arch-ivybridge/pch.h b/arch/x86/include/asm/arch-ivybridge/pch.h index 21df083..31437c8 100644 --- a/arch/x86/include/asm/arch-ivybridge/pch.h +++ b/arch/x86/include/asm/arch-ivybridge/pch.h @@ -105,6 +105,8 @@ void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue); #define GPIO_ROUT 0xb8 #define LPC_IO_DEC 0x80 /* IO Decode Ranges Register */ +#define COMB_DEC_RANGE (1 << 4) /* 0x2f8-0x2ff (COM2) */ +#define COMA_DEC_RANGE (0 << 0) /* 0x3f8-0x3ff (COM1) */ #define LPC_EN 0x82 /* LPC IF Enables Register */ #define CNF2_LPC_EN (1 << 13) /* 0x4e/0x4f */ #define CNF1_LPC_EN (1 << 12) /* 0x2e/0x2f */ @@ -121,6 +123,14 @@ void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue); #define LPC_GEN3_DEC 0x8c /* LPC IF Generic Decode Range 3 */ #define LPC_GEN4_DEC 0x90 /* LPC IF Generic Decode Range 4 */ #define LPC_GENX_DEC(x) (0x84 + 4 * (x)) +#define GEN_DEC_RANGE_256B 0xfc0000 /* 256 Bytes */ +#define GEN_DEC_RANGE_128B 0x7c0000 /* 128 Bytes */ +#define GEN_DEC_RANGE_64B 0x3c0000 /* 64 Bytes */ +#define GEN_DEC_RANGE_32B 0x1c0000 /* 32 Bytes */ +#define GEN_DEC_RANGE_16B 0x0c0000 /* 16 Bytes */ +#define GEN_DEC_RANGE_8B 0x040000 /* 8 Bytes */ +#define GEN_DEC_RANGE_4B 0x000000 /* 4 Bytes */ +#define GEN_DEC_RANGE_EN (1 << 0) /* Range Enable */ /* PCI Configuration Space (D31:F1): IDE */ #define PCH_IDE_DEV PCI_BDF(0, 0x1f, 1) |