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| author | Bin Meng <bmeng.cn@gmail.com> | 2015-06-03 09:20:06 +0800 |
|---|---|---|
| committer | Simon Glass <sjg@chromium.org> | 2015-06-04 03:03:18 -0600 |
| commit | 5c564226fc8948e435edea8eb8c5c4afbc5edef1 (patch) | |
| tree | 416ea4a8cc9e61959ff940784ee986ee1097e4b5 /arch/x86/dts/qemu-x86_q35.dts | |
| parent | f2653e8dd92229328480da35c26e6f9fbfec4381 (diff) | |
| download | u-boot-imx-5c564226fc8948e435edea8eb8c5c4afbc5edef1.zip u-boot-imx-5c564226fc8948e435edea8eb8c5c4afbc5edef1.tar.gz u-boot-imx-5c564226fc8948e435edea8eb8c5c4afbc5edef1.tar.bz2 | |
x86: qemu: Implement PIRQ routing
Support QEMU PIRQ routing via device tree on both i440fx and q35
platforms. With this commit, Linux booting on QEMU from U-Boot
has working ATA/SATA, USB and ethernet.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Diffstat (limited to 'arch/x86/dts/qemu-x86_q35.dts')
| -rw-r--r-- | arch/x86/dts/qemu-x86_q35.dts | 32 |
1 files changed, 32 insertions, 0 deletions
diff --git a/arch/x86/dts/qemu-x86_q35.dts b/arch/x86/dts/qemu-x86_q35.dts index 02a483c..c259f2a 100644 --- a/arch/x86/dts/qemu-x86_q35.dts +++ b/arch/x86/dts/qemu-x86_q35.dts @@ -6,6 +6,18 @@ /dts-v1/; +#include <dt-bindings/interrupt-router/intel-irq.h> + +/* ICH9 IRQ router has discrete PIRQ control registers */ +#undef PIRQE +#undef PIRQF +#undef PIRQG +#undef PIRQH +#define PIRQE 8 +#define PIRQF 9 +#define PIRQG 10 +#define PIRQH 11 + /include/ "skeleton.dtsi" /include/ "serial.dtsi" @@ -30,6 +42,26 @@ ranges = <0x02000000 0x0 0xc0000000 0xc0000000 0 0x10000000 0x42000000 0x0 0xd0000000 0xd0000000 0 0x10000000 0x01000000 0x0 0x2000 0x2000 0 0xe000>; + + irq-router@1f,0 { + reg = <0x0000f800 0 0 0 0>; + compatible = "intel,irq-router"; + intel,pirq-config = "pci"; + intel,pirq-link = <0x60 8>; + intel,pirq-mask = <0x0e40>; + intel,pirq-routing = < + /* e1000 NIC */ + PCI_BDF(0, 2, 0) INTA PIRQG + /* ICH9 UHCI */ + PCI_BDF(0, 29, 0) INTA PIRQA + PCI_BDF(0, 29, 1) INTB PIRQB + PCI_BDF(0, 29, 2) INTC PIRQC + /* ICH9 EHCI */ + PCI_BDF(0, 29, 7) INTD PIRQD + /* ICH9 SATA */ + PCI_BDF(0, 31, 2) INTA PIRQA + >; + }; }; }; |