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| author | Simon Glass <sjg@chromium.org> | 2014-11-12 22:42:15 -0700 |
|---|---|---|
| committer | Simon Glass <sjg@chromium.org> | 2014-11-21 07:34:12 +0100 |
| commit | 2b6051541b562b72d2cf784376a84552da18318d (patch) | |
| tree | c21b6ae92539eb63628f15b52044dd164471aed7 /arch/x86/dts/link.dts | |
| parent | 6fb3b72e8745073465b4a5875b7750cc43cbd1af (diff) | |
| download | u-boot-imx-2b6051541b562b72d2cf784376a84552da18318d.zip u-boot-imx-2b6051541b562b72d2cf784376a84552da18318d.tar.gz u-boot-imx-2b6051541b562b72d2cf784376a84552da18318d.tar.bz2 | |
x86: ivybridge: Add early LPC init so that serial works
The PCH (Platform Controller Hub) includes an LPC (Low Pin Count) device
which provides a serial port. This is accessible on Chromebooks, so enable
it early in the boot process.
Signed-off-by: Simon Glass <sjg@chromium.org>
Diffstat (limited to 'arch/x86/dts/link.dts')
| -rw-r--r-- | arch/x86/dts/link.dts | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/x86/dts/link.dts b/arch/x86/dts/link.dts index f2fcb39..63933aa 100644 --- a/arch/x86/dts/link.dts +++ b/arch/x86/dts/link.dts @@ -53,6 +53,7 @@ compatible = "intel,lpc"; #address-cells = <1>; #size-cells = <1>; + gen-dec = <0x800 0xfc 0x900 0xfc>; cros-ec@200 { compatible = "google,cros-ec"; reg = <0x204 1 0x200 1 0x880 0x80>; |