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authorBin Meng <bmeng.cn@gmail.com>2015-07-22 01:21:14 -0700
committerSimon Glass <sjg@chromium.org>2015-07-28 10:36:25 -0600
commit9830d2ebb4f1683ff7f50b3420374a1843839378 (patch)
treef00ef30f3dbb7b151bb0b27db32bba0ef7904e92 /arch/x86/cpu
parenta8ebf283e98d0eda0b7c76647cdcd3f36f34837c (diff)
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x86: qemu: Turn on PCIe ECAM address range decoding on Q35
Turn on PCIe ECAM address range decoding on Q35. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
Diffstat (limited to 'arch/x86/cpu')
-rw-r--r--arch/x86/cpu/qemu/pci.c4
1 files changed, 4 insertions, 0 deletions
diff --git a/arch/x86/cpu/qemu/pci.c b/arch/x86/cpu/qemu/pci.c
index acbd922..2e94456 100644
--- a/arch/x86/cpu/qemu/pci.c
+++ b/arch/x86/cpu/qemu/pci.c
@@ -90,6 +90,10 @@ int board_pci_post_scan(struct pci_controller *hose)
xbcs = x86_pci_read_config16(PIIX_ISA, XBCS);
xbcs |= APIC_EN;
x86_pci_write_config16(PIIX_ISA, XBCS, xbcs);
+ } else {
+ /* Configure PCIe ECAM base address */
+ x86_pci_write_config32(PCI_BDF(0, 0, 0), PCIEX_BAR,
+ CONFIG_PCIE_ECAM_BASE | BAR_EN);
}
/*