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authorTom Rini <trini@konsulko.com>2015-07-15 10:41:20 -0400
committerTom Rini <trini@konsulko.com>2015-07-15 10:41:20 -0400
commit605e15db2b54302364a2528d3c6604fbc57be846 (patch)
tree1a1e344964bff1719939183124d66a71e7ca7731 /arch/x86/cpu/queensbay
parent4905dfc65d9a17083727865302d2cf633c15c911 (diff)
parentf110da9984c0aa0aba9e1c4178b67b7abecf7e8d (diff)
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Merge git://git.denx.de/u-boot-x86
Diffstat (limited to 'arch/x86/cpu/queensbay')
-rw-r--r--arch/x86/cpu/queensbay/Kconfig4
-rw-r--r--arch/x86/cpu/queensbay/tnc.c13
2 files changed, 11 insertions, 6 deletions
diff --git a/arch/x86/cpu/queensbay/Kconfig b/arch/x86/cpu/queensbay/Kconfig
index 397e599..fbf85f2 100644
--- a/arch/x86/cpu/queensbay/Kconfig
+++ b/arch/x86/cpu/queensbay/Kconfig
@@ -38,4 +38,8 @@ config CMC_ADDR
The default base address of 0xfffb0000 indicates that the binary must
be located at offset 0xb0000 from the beginning of a 1MB flash device.
+config CPU_ADDR_BITS
+ int
+ default 32
+
endif
diff --git a/arch/x86/cpu/queensbay/tnc.c b/arch/x86/cpu/queensbay/tnc.c
index 873de7b..d27b2d9 100644
--- a/arch/x86/cpu/queensbay/tnc.c
+++ b/arch/x86/cpu/queensbay/tnc.c
@@ -69,17 +69,18 @@ void cpu_irq_init(void)
* Route TunnelCreek PCI device interrupt pin to PIRQ
*
* Since PCIe downstream ports received INTx are routed to PIRQ
- * A/B/C/D directly and not configurable, we route internal PCI
- * device's INTx to PIRQ E/F/G/H.
+ * A/B/C/D directly and not configurable, we have to route PCIe
+ * root ports' INTx to PIRQ A/B/C/D as well. For other devices
+ * on TunneCreek, route them to PIRQ E/F/G/H.
*/
writew(PIRQE, &rcba->d02ir);
writew(PIRQF, &rcba->d03ir);
writew(PIRQG, &rcba->d27ir);
writew(PIRQH, &rcba->d31ir);
- writew(PIRQE, &rcba->d23ir);
- writew(PIRQF, &rcba->d24ir);
- writew(PIRQG, &rcba->d25ir);
- writew(PIRQH, &rcba->d26ir);
+ writew(PIRQA, &rcba->d23ir);
+ writew(PIRQB, &rcba->d24ir);
+ writew(PIRQC, &rcba->d25ir);
+ writew(PIRQD, &rcba->d26ir);
}
int arch_misc_init(void)