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| author | Bin Meng <bmeng.cn@gmail.com> | 2015-05-25 22:35:04 +0800 |
|---|---|---|
| committer | Simon Glass <sjg@chromium.org> | 2015-06-04 02:39:39 -0600 |
| commit | 9c7dea602edd9027848d312e9b3b69f06c15f163 (patch) | |
| tree | 4893732c170a3a889b819482f7003491ecbac11c /arch/x86/cpu/queensbay/tnc.c | |
| parent | 2aa3a7fb1c24afd4c0e12360acccf3234d8fe019 (diff) | |
| download | u-boot-imx-9c7dea602edd9027848d312e9b3b69f06c15f163.zip u-boot-imx-9c7dea602edd9027848d312e9b3b69f06c15f163.tar.gz u-boot-imx-9c7dea602edd9027848d312e9b3b69f06c15f163.tar.bz2 | |
x86: Refactor PIRQ routing support
PIRQ routing is pretty much common in Intel chipset. It has several
PIRQ links (normally 8) and corresponding registers (either in PCI
configuration space or memory-mapped IBASE) to configure the legacy
8259 IRQ vector mapping. Refactor current Queensbay PIRQ routing
support using device tree and move it to a common place, so that we
can easily add PIRQ routing support on a new platform.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Diffstat (limited to 'arch/x86/cpu/queensbay/tnc.c')
| -rw-r--r-- | arch/x86/cpu/queensbay/tnc.c | 39 |
1 files changed, 38 insertions, 1 deletions
diff --git a/arch/x86/cpu/queensbay/tnc.c b/arch/x86/cpu/queensbay/tnc.c index b46a7e9..873de7b 100644 --- a/arch/x86/cpu/queensbay/tnc.c +++ b/arch/x86/cpu/queensbay/tnc.c @@ -6,10 +6,11 @@ #include <common.h> #include <asm/io.h> +#include <asm/irq.h> #include <asm/pci.h> #include <asm/post.h> #include <asm/arch/device.h> -#include <asm/arch/irq.h> +#include <asm/arch/tnc.h> #include <asm/fsp/fsp_support.h> #include <asm/processor.h> @@ -45,6 +46,42 @@ int arch_cpu_init(void) return 0; } +void cpu_irq_init(void) +{ + struct tnc_rcba *rcba; + u32 base; + + base = x86_pci_read_config32(TNC_LPC, LPC_RCBA); + base &= ~MEM_BAR_EN; + rcba = (struct tnc_rcba *)base; + + /* Make sure all internal PCI devices are using INTA */ + writel(INTA, &rcba->d02ip); + writel(INTA, &rcba->d03ip); + writel(INTA, &rcba->d27ip); + writel(INTA, &rcba->d31ip); + writel(INTA, &rcba->d23ip); + writel(INTA, &rcba->d24ip); + writel(INTA, &rcba->d25ip); + writel(INTA, &rcba->d26ip); + + /* + * Route TunnelCreek PCI device interrupt pin to PIRQ + * + * Since PCIe downstream ports received INTx are routed to PIRQ + * A/B/C/D directly and not configurable, we route internal PCI + * device's INTx to PIRQ E/F/G/H. + */ + writew(PIRQE, &rcba->d02ir); + writew(PIRQF, &rcba->d03ir); + writew(PIRQG, &rcba->d27ir); + writew(PIRQH, &rcba->d31ir); + writew(PIRQE, &rcba->d23ir); + writew(PIRQF, &rcba->d24ir); + writew(PIRQG, &rcba->d25ir); + writew(PIRQH, &rcba->d26ir); +} + int arch_misc_init(void) { pirq_init(); |