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| author | Tom Rini <trini@konsulko.com> | 2016-05-23 18:32:47 -0400 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2016-05-23 18:32:47 -0400 |
| commit | 6d54868eeb2697c9a905c4d3521efbacc44c5258 (patch) | |
| tree | 6ad3ae03a0083d1a50a6152bd6dcad5630ce7823 /arch/x86/cpu/qemu/qemu.c | |
| parent | d7d000311285e4b8d11e089ca13ea456a01be3b8 (diff) | |
| parent | 8216b11cdd50515fbc423a4b2709a00865b8621d (diff) | |
| download | u-boot-imx-6d54868eeb2697c9a905c4d3521efbacc44c5258.zip u-boot-imx-6d54868eeb2697c9a905c4d3521efbacc44c5258.tar.gz u-boot-imx-6d54868eeb2697c9a905c4d3521efbacc44c5258.tar.bz2 | |
Merge branch 'master' of git://git.denx.de/u-boot-x86
Diffstat (limited to 'arch/x86/cpu/qemu/qemu.c')
| -rw-r--r-- | arch/x86/cpu/qemu/qemu.c | 50 |
1 files changed, 48 insertions, 2 deletions
diff --git a/arch/x86/cpu/qemu/qemu.c b/arch/x86/cpu/qemu/qemu.c index 7ad0ee4..680e558 100644 --- a/arch/x86/cpu/qemu/qemu.c +++ b/arch/x86/cpu/qemu/qemu.c @@ -6,15 +6,59 @@ #include <common.h> #include <pci.h> +#include <qfw.h> #include <asm/irq.h> #include <asm/post.h> #include <asm/processor.h> #include <asm/arch/device.h> #include <asm/arch/qemu.h> -#include <asm/fw_cfg.h> static bool i440fx; +#ifdef CONFIG_QFW + +/* on x86, the qfw registers are all IO ports */ +#define FW_CONTROL_PORT 0x510 +#define FW_DATA_PORT 0x511 +#define FW_DMA_PORT_LOW 0x514 +#define FW_DMA_PORT_HIGH 0x518 + +static void qemu_x86_fwcfg_read_entry_pio(uint16_t entry, + uint32_t size, void *address) +{ + uint32_t i = 0; + uint8_t *data = address; + + /* + * writting FW_CFG_INVALID will cause read operation to resume at + * last offset, otherwise read will start at offset 0 + * + * Note: on platform where the control register is IO port, the + * endianness is little endian. + */ + if (entry != FW_CFG_INVALID) + outw(cpu_to_le16(entry), FW_CONTROL_PORT); + + /* the endianness of data register is string-preserving */ + while (size--) + data[i++] = inb(FW_DATA_PORT); +} + +static void qemu_x86_fwcfg_read_entry_dma(struct fw_cfg_dma_access *dma) +{ + /* the DMA address register is big endian */ + outl(cpu_to_be32((uint32_t)dma), FW_DMA_PORT_HIGH); + + while (be32_to_cpu(dma->control) & ~FW_CFG_DMA_ERROR) + __asm__ __volatile__ ("pause"); +} + +static struct fw_cfg_arch_ops fwcfg_x86_ops = { + .arch_read_pio = qemu_x86_fwcfg_read_entry_pio, + .arch_read_dma = qemu_x86_fwcfg_read_entry_dma +}; +#endif + static void enable_pm_piix(void) { u8 en; @@ -88,7 +132,9 @@ static void qemu_chipset_init(void) enable_pm_ich9(); } - qemu_fwcfg_init(); +#ifdef CONFIG_QFW + qemu_fwcfg_init(&fwcfg_x86_ops); +#endif } int arch_cpu_init(void) |