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| author | Simon Glass <sjg@chromium.org> | 2016-02-11 13:23:26 -0700 |
|---|---|---|
| committer | Simon Glass <sjg@chromium.org> | 2016-03-14 15:34:50 -0600 |
| commit | 3f603cbbb8e175e545d6037a783e1ef82bab30f9 (patch) | |
| tree | c3122b2be426be9bcfd3285bda86cb175fb9aaeb /arch/x86/cpu/ivybridge | |
| parent | b06750501f5c0eef7fef094f13d2f2e313c60b79 (diff) | |
| download | u-boot-imx-3f603cbbb8e175e545d6037a783e1ef82bab30f9.zip u-boot-imx-3f603cbbb8e175e545d6037a783e1ef82bab30f9.tar.gz u-boot-imx-3f603cbbb8e175e545d6037a783e1ef82bab30f9.tar.bz2 | |
dm: Use uclass_first_device_err() where it is useful
Use this new function in places where it simplifies the code.
Signed-off-by: Simon Glass <sjg@chromium.org>
Diffstat (limited to 'arch/x86/cpu/ivybridge')
| -rw-r--r-- | arch/x86/cpu/ivybridge/cpu.c | 14 | ||||
| -rw-r--r-- | arch/x86/cpu/ivybridge/gma.c | 6 | ||||
| -rw-r--r-- | arch/x86/cpu/ivybridge/sata.c | 4 | ||||
| -rw-r--r-- | arch/x86/cpu/ivybridge/sdram.c | 4 |
4 files changed, 10 insertions, 18 deletions
diff --git a/arch/x86/cpu/ivybridge/cpu.c b/arch/x86/cpu/ivybridge/cpu.c index 948833c..5d839a7 100644 --- a/arch/x86/cpu/ivybridge/cpu.c +++ b/arch/x86/cpu/ivybridge/cpu.c @@ -104,9 +104,9 @@ int arch_cpu_init_dm(void) /* TODO(sjg@chromium.org): Get rid of gd->hose */ gd->hose = hose; - ret = uclass_first_device(UCLASS_LPC, &dev); - if (!dev) - return -ENODEV; + ret = uclass_first_device_err(UCLASS_LPC, &dev); + if (ret) + return ret; /* * We should do as little as possible before the serial console is @@ -210,11 +210,9 @@ int print_cpuinfo(void) /* Early chipset init required before RAM init can work */ uclass_first_device(UCLASS_NORTHBRIDGE, &dev); - ret = uclass_first_device(UCLASS_LPC, &lpc); + ret = uclass_first_device_err(UCLASS_LPC, &lpc); if (ret) return ret; - if (!dev) - return -ENODEV; /* Cause the SATA device to do its early init */ uclass_first_device(UCLASS_DISK, &dev); @@ -236,11 +234,9 @@ int print_cpuinfo(void) post_code(POST_EARLY_INIT); /* Enable SPD ROMs and DDR-III DRAM */ - ret = uclass_first_device(UCLASS_I2C, &dev); + ret = uclass_first_device_err(UCLASS_I2C, &dev); if (ret) return ret; - if (!dev) - return -ENODEV; /* Prepare USB controller early in S3 resume */ if (boot_mode == PEI_BOOT_RESUME) diff --git a/arch/x86/cpu/ivybridge/gma.c b/arch/x86/cpu/ivybridge/gma.c index 3b6291e..91a57f9 100644 --- a/arch/x86/cpu/ivybridge/gma.c +++ b/arch/x86/cpu/ivybridge/gma.c @@ -812,9 +812,9 @@ int gma_func0_init(struct udevice *dev) writew(0x0010, RCB_REG(DISPBDF)); setbits_le32(RCB_REG(FD2), PCH_ENABLE_DBDF); - ret = uclass_first_device(UCLASS_NORTHBRIDGE, &nbridge); - if (!nbridge) - return -ENODEV; + ret = uclass_first_device_err(UCLASS_NORTHBRIDGE, &nbridge); + if (ret) + return ret; rev = bridge_silicon_revision(nbridge); sandybridge_setup_graphics(nbridge, dev); diff --git a/arch/x86/cpu/ivybridge/sata.c b/arch/x86/cpu/ivybridge/sata.c index a59d9ed..da6455b 100644 --- a/arch/x86/cpu/ivybridge/sata.c +++ b/arch/x86/cpu/ivybridge/sata.c @@ -229,11 +229,9 @@ static int bd82x6x_sata_probe(struct udevice *dev) struct udevice *pch; int ret; - ret = uclass_first_device(UCLASS_PCH, &pch); + ret = uclass_first_device_err(UCLASS_PCH, &pch); if (ret) return ret; - if (!pch) - return -ENODEV; if (!(gd->flags & GD_FLG_RELOC)) bd82x6x_sata_enable(dev); diff --git a/arch/x86/cpu/ivybridge/sdram.c b/arch/x86/cpu/ivybridge/sdram.c index e23c422..0ebcc2c 100644 --- a/arch/x86/cpu/ivybridge/sdram.c +++ b/arch/x86/cpu/ivybridge/sdram.c @@ -736,11 +736,9 @@ int dram_init(void) struct udevice *dev, *me_dev; int ret; - ret = uclass_first_device(UCLASS_NORTHBRIDGE, &dev); + ret = uclass_first_device_err(UCLASS_NORTHBRIDGE, &dev); if (ret) return ret; - if (!dev) - return -ENODEV; ret = syscon_get_by_driver_data(X86_SYSCON_ME, &me_dev); if (ret) return ret; |