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| author | Bin Meng <bmeng.cn@gmail.com> | 2015-01-06 22:14:23 +0800 |
|---|---|---|
| committer | Simon Glass <sjg@chromium.org> | 2015-01-13 07:25:05 -0800 |
| commit | cdcc17d73dcbc40ccc74af98d914fbd61df4b85e (patch) | |
| tree | 6b2a33e0111f2ef33e9228ee6a4bf66ac2058d79 /arch/x86/cpu/coreboot | |
| parent | 48a223e4ba0a7fec5940cccf7950b656e4f7cbed (diff) | |
| download | u-boot-imx-cdcc17d73dcbc40ccc74af98d914fbd61df4b85e.zip u-boot-imx-cdcc17d73dcbc40ccc74af98d914fbd61df4b85e.tar.gz u-boot-imx-cdcc17d73dcbc40ccc74af98d914fbd61df4b85e.tar.bz2 | |
x86: coreboot: Configure pci memory regions
Configure coreboot pci memory regions so that pci device drivers
could work correctly.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Diffstat (limited to 'arch/x86/cpu/coreboot')
| -rw-r--r-- | arch/x86/cpu/coreboot/pci.c | 30 |
1 files changed, 28 insertions, 2 deletions
diff --git a/arch/x86/cpu/coreboot/pci.c b/arch/x86/cpu/coreboot/pci.c index 6a3dd93..c9983f1 100644 --- a/arch/x86/cpu/coreboot/pci.c +++ b/arch/x86/cpu/coreboot/pci.c @@ -13,6 +13,8 @@ #include <pci.h> #include <asm/pci.h> +DECLARE_GLOBAL_DATA_PTR; + static void config_pci_bridge(struct pci_controller *hose, pci_dev_t dev, struct pci_config_table *table) { @@ -35,7 +37,31 @@ void board_pci_setup_hose(struct pci_controller *hose) hose->first_busno = 0; hose->last_busno = 0; - pci_set_region(hose->regions + 0, 0x0, 0x0, 0xffffffff, + /* PCI memory space */ + pci_set_region(hose->regions + 0, + CONFIG_PCI_MEM_BUS, + CONFIG_PCI_MEM_PHYS, + CONFIG_PCI_MEM_SIZE, PCI_REGION_MEM); - hose->region_count = 1; + + /* PCI IO space */ + pci_set_region(hose->regions + 1, + CONFIG_PCI_IO_BUS, + CONFIG_PCI_IO_PHYS, + CONFIG_PCI_IO_SIZE, + PCI_REGION_IO); + + pci_set_region(hose->regions + 2, + CONFIG_PCI_PREF_BUS, + CONFIG_PCI_PREF_PHYS, + CONFIG_PCI_PREF_SIZE, + PCI_REGION_PREFETCH); + + pci_set_region(hose->regions + 3, + 0, + 0, + gd->ram_size, + PCI_REGION_MEM | PCI_REGION_SYS_MEMORY); + + hose->region_count = 4; } |