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author | Simon Glass <sjg@chromium.org> | 2015-03-05 12:25:32 -0700 |
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committer | Simon Glass <sjg@chromium.org> | 2015-04-18 11:11:09 -0600 |
commit | 801f4f1bbc5ae838cdd50df09895dc275726d23a (patch) | |
tree | 0396a350136990d52eef97906aac18de85e6d4f7 /arch/x86/cpu/coreboot | |
parent | a219daeafef4df1b219db68c80116d82113c82b2 (diff) | |
download | u-boot-imx-801f4f1bbc5ae838cdd50df09895dc275726d23a.zip u-boot-imx-801f4f1bbc5ae838cdd50df09895dc275726d23a.tar.gz u-boot-imx-801f4f1bbc5ae838cdd50df09895dc275726d23a.tar.bz2 |
dm: x86: pci: Convert coreboot to use driver model for pci
Move coreboot-x86 over to driver model for PCI.
Signed-off-by: Simon Glass <sjg@chromium.org>
Diffstat (limited to 'arch/x86/cpu/coreboot')
-rw-r--r-- | arch/x86/cpu/coreboot/pci.c | 63 |
1 files changed, 16 insertions, 47 deletions
diff --git a/arch/x86/cpu/coreboot/pci.c b/arch/x86/cpu/coreboot/pci.c index c9983f1..fa415dd 100644 --- a/arch/x86/cpu/coreboot/pci.c +++ b/arch/x86/cpu/coreboot/pci.c @@ -10,58 +10,27 @@ */ #include <common.h> +#include <dm.h> +#include <errno.h> #include <pci.h> +#include <asm/io.h> #include <asm/pci.h> DECLARE_GLOBAL_DATA_PTR; -static void config_pci_bridge(struct pci_controller *hose, pci_dev_t dev, - struct pci_config_table *table) -{ - u8 secondary; - hose->read_byte(hose, dev, PCI_SECONDARY_BUS, &secondary); - hose->last_busno = max(hose->last_busno, (int)secondary); - pci_hose_scan_bus(hose, secondary); -} - -static struct pci_config_table pci_coreboot_config_table[] = { - /* vendor, device, class, bus, dev, func */ - { PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_BRIDGE_PCI, - PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, &config_pci_bridge }, - {} +static const struct dm_pci_ops pci_x86_ops = { + .read_config = pci_x86_read_config, + .write_config = pci_x86_write_config, }; -void board_pci_setup_hose(struct pci_controller *hose) -{ - hose->config_table = pci_coreboot_config_table; - hose->first_busno = 0; - hose->last_busno = 0; - - /* PCI memory space */ - pci_set_region(hose->regions + 0, - CONFIG_PCI_MEM_BUS, - CONFIG_PCI_MEM_PHYS, - CONFIG_PCI_MEM_SIZE, - PCI_REGION_MEM); - - /* PCI IO space */ - pci_set_region(hose->regions + 1, - CONFIG_PCI_IO_BUS, - CONFIG_PCI_IO_PHYS, - CONFIG_PCI_IO_SIZE, - PCI_REGION_IO); - - pci_set_region(hose->regions + 2, - CONFIG_PCI_PREF_BUS, - CONFIG_PCI_PREF_PHYS, - CONFIG_PCI_PREF_SIZE, - PCI_REGION_PREFETCH); - - pci_set_region(hose->regions + 3, - 0, - 0, - gd->ram_size, - PCI_REGION_MEM | PCI_REGION_SYS_MEMORY); +static const struct udevice_id pci_x86_ids[] = { + { .compatible = "pci-x86" }, + { } +}; - hose->region_count = 4; -} +U_BOOT_DRIVER(pci_x86_drv) = { + .name = "pci_x86", + .id = UCLASS_PCI, + .of_match = pci_x86_ids, + .ops = &pci_x86_ops, +}; |