diff options
author | Simon Glass <sjg@chromium.org> | 2014-11-12 22:42:11 -0700 |
---|---|---|
committer | Simon Glass <sjg@chromium.org> | 2014-11-21 07:34:11 +0100 |
commit | d188b18f65417a0a6698c43926e3c66b134195b8 (patch) | |
tree | 10ed6a3acef604ebce493a84f633540bd2a5c3c8 /arch/x86/cpu/coreboot/pci.c | |
parent | 70a09c6c3dc25b200a9d0475afcf5dfc9836b18e (diff) | |
download | u-boot-imx-d188b18f65417a0a6698c43926e3c66b134195b8.zip u-boot-imx-d188b18f65417a0a6698c43926e3c66b134195b8.tar.gz u-boot-imx-d188b18f65417a0a6698c43926e3c66b134195b8.tar.bz2 |
x86: Refactor PCI to permit alternate init
We want access PCI earlier in the init sequence, so refactor the code so
that it does not require use of a BSS variable to work. This will allow us
to use early malloc() to store information about a PCI hose.
Common PCI code moves to arch/x86/cpu/pci.c and a new
board_pci_setup_hose() function is provided by boards to set up the (single)
hose used by that board.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Diffstat (limited to 'arch/x86/cpu/coreboot/pci.c')
-rw-r--r-- | arch/x86/cpu/coreboot/pci.c | 22 |
1 files changed, 7 insertions, 15 deletions
diff --git a/arch/x86/cpu/coreboot/pci.c b/arch/x86/cpu/coreboot/pci.c index 33f16a3..4778f71 100644 --- a/arch/x86/cpu/coreboot/pci.c +++ b/arch/x86/cpu/coreboot/pci.c @@ -13,8 +13,6 @@ #include <pci.h> #include <asm/pci.h> -static struct pci_controller coreboot_hose; - static void config_pci_bridge(struct pci_controller *hose, pci_dev_t dev, struct pci_config_table *table) { @@ -31,19 +29,13 @@ static struct pci_config_table pci_coreboot_config_table[] = { {} }; -void pci_init_board(void) +void board_pci_setup_hose(struct pci_controller *hose) { - coreboot_hose.config_table = pci_coreboot_config_table; - coreboot_hose.first_busno = 0; - coreboot_hose.last_busno = 0; - - pci_set_region(coreboot_hose.regions + 0, 0x0, 0x0, 0xffffffff, - PCI_REGION_MEM); - coreboot_hose.region_count = 1; - - pci_setup_type1(&coreboot_hose); - - pci_register_hose(&coreboot_hose); + hose->config_table = pci_coreboot_config_table; + hose->first_busno = 0; + hose->last_busno = 0; - pci_hose_scan(&coreboot_hose); + pci_set_region(hose->regions + 0, 0x0, 0x0, 0xffffffff, + PCI_REGION_MEM); + hose->region_count = 1; } |