Merge branch 'master' of git://git.denx.de/u-boot

17 files changed, 81 insertions, 302 deletions

diff --git a/arch/powerpc/cpu/mpc5xxx/Kconfig b/arch/powerpc/cpu/mpc5xxx/Kconfig
index e2e9cb7..9da00da 100644
--- a/arch/powerpc/cpu/mpc5xxx/Kconfig
+++ b/arch/powerpc/cpu/mpc5xxx/Kconfig
@@ -26,9 +26,6 @@ config TARGET_CM5200
 config TARGET_GALAXY5200
 	bool "Support galaxy5200"
 
-config TARGET_ICECUBE
-	bool "Support IceCube"
-
 config TARGET_INKA4X0
 	bool "Support inka4x0"
 
@@ -44,24 +41,9 @@ config TARGET_MOTIONPRO
 config TARGET_MUNICES
 	bool "Support munices"
 
-config TARGET_PM520
-	bool "Support PM520"
-
-config TARGET_TOTAL5200
-	bool "Support Total5200"
-
 config TARGET_V38B
 	bool "Support v38b"
 
-config TARGET_CPCI5200
-	bool "Support cpci5200"
-
-config TARGET_MECP5200
-	bool "Support mecp5200"
-
-config TARGET_PF5200
-	bool "Support pf5200"
-
 config TARGET_O2D
 	bool "Support O2D"
 
@@ -105,11 +87,7 @@ source "board/a4m072/Kconfig"
 source "board/bc3450/Kconfig"
 source "board/canmb/Kconfig"
 source "board/cm5200/Kconfig"
-source "board/esd/cpci5200/Kconfig"
-source "board/esd/mecp5200/Kconfig"
-source "board/esd/pf5200/Kconfig"
 source "board/galaxy5200/Kconfig"
-source "board/icecube/Kconfig"
 source "board/ifm/o2dnt2/Kconfig"
 source "board/inka4x0/Kconfig"
 source "board/intercontrol/digsy_mtc/Kconfig"
@@ -118,8 +96,6 @@ source "board/jupiter/Kconfig"
 source "board/motionpro/Kconfig"
 source "board/munices/Kconfig"
 source "board/phytec/pcm030/Kconfig"
-source "board/pm520/Kconfig"
-source "board/total5200/Kconfig"
 source "board/tqc/tqm5200/Kconfig"
 source "board/v38b/Kconfig"
 
diff --git a/arch/powerpc/cpu/mpc5xxx/pci_mpc5200.c b/arch/powerpc/cpu/mpc5xxx/pci_mpc5200.c
index a89d5fd..70b7e6e 100644
--- a/arch/powerpc/cpu/mpc5xxx/pci_mpc5200.c
+++ b/arch/powerpc/cpu/mpc5xxx/pci_mpc5200.c
@@ -33,21 +33,7 @@ static int mpc5200_read_config_dword(struct pci_controller *hose,
 	*(volatile u32 *)MPC5XXX_PCI_CAR = (1 << 31) | dev | offset;
 	eieio();
 	udelay(10);
-#if (defined CONFIG_PF5200 || defined CONFIG_CPCI5200)
-	if (dev & 0x00ff0000) {
-		u32 val;
-		val  = in_le16((volatile u16 *)(CONFIG_PCI_IO_PHYS+2));
-		udelay(10);
-		val = val << 16;
-		val |= in_le16((volatile u16 *)(CONFIG_PCI_IO_PHYS+0));
-		*value = val;
-	} else {
-		*value = in_le32((volatile u32 *)CONFIG_PCI_IO_PHYS);
-	}
-	udelay(10);
-#else
 	*value = in_le32((volatile u32 *)CONFIG_PCI_IO_PHYS);
-#endif
 	eieio();
 	*(volatile u32 *)MPC5XXX_PCI_CAR = 0;
 	udelay(10);
diff --git a/arch/powerpc/cpu/mpc83xx/Kconfig b/arch/powerpc/cpu/mpc83xx/Kconfig
index 69a600c..4d6cb09 100644
--- a/arch/powerpc/cpu/mpc83xx/Kconfig
+++ b/arch/powerpc/cpu/mpc83xx/Kconfig
@@ -41,12 +41,6 @@ config TARGET_MPC8349EMDS
 config TARGET_MPC8349ITX
 	bool "Support MPC8349ITX"
 
-config TARGET_MPC8360EMDS
-	bool "Support MPC8360EMDS"
-
-config TARGET_MPC8360ERDK
-	bool "Support MPC8360ERDK"
-
 config TARGET_MPC837XEMDS
 	bool "Support MPC837XEMDS"
 
@@ -81,8 +75,6 @@ source "board/freescale/mpc8323erdb/Kconfig"
 source "board/freescale/mpc832xemds/Kconfig"
 source "board/freescale/mpc8349emds/Kconfig"
 source "board/freescale/mpc8349itx/Kconfig"
-source "board/freescale/mpc8360emds/Kconfig"
-source "board/freescale/mpc8360erdk/Kconfig"
 source "board/freescale/mpc837xemds/Kconfig"
 source "board/freescale/mpc837xerdb/Kconfig"
 source "board/ids/ids8313/Kconfig"
diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig
index 7501eb4..adb5bd3 100644
--- a/arch/powerpc/cpu/mpc85xx/Kconfig
+++ b/arch/powerpc/cpu/mpc85xx/Kconfig
@@ -85,11 +85,6 @@ config TARGET_P1022DS
 config TARGET_P1023RDB
 	bool "Support P1023RDB"
 
-config TARGET_P1_P2_RDB
-	bool "Support P1_P2_RDB"
-	select SUPPORT_SPL
-	select SUPPORT_TPL
-
 config TARGET_P1_P2_RDB_PC
 	bool "Support p1_p2_rdb_pc"
 	select SUPPORT_SPL
@@ -98,12 +93,6 @@ config TARGET_P1_P2_RDB_PC
 config TARGET_P1_TWR
 	bool "Support p1_twr"
 
-config TARGET_P2020COME
-	bool "Support P2020COME"
-
-config TARGET_P2020DS
-	bool "Support P2020DS"
-
 config TARGET_P2041RDB
 	bool "Support P2041RDB"
 
@@ -184,11 +173,8 @@ source "board/freescale/mpc8572ds/Kconfig"
 source "board/freescale/p1010rdb/Kconfig"
 source "board/freescale/p1022ds/Kconfig"
 source "board/freescale/p1023rdb/Kconfig"
-source "board/freescale/p1_p2_rdb/Kconfig"
 source "board/freescale/p1_p2_rdb_pc/Kconfig"
 source "board/freescale/p1_twr/Kconfig"
-source "board/freescale/p2020come/Kconfig"
-source "board/freescale/p2020ds/Kconfig"
 source "board/freescale/p2041rdb/Kconfig"
 source "board/freescale/qemu-ppce500/Kconfig"
 source "board/freescale/t102xqds/Kconfig"
diff --git a/arch/powerpc/cpu/mpc85xx/b4860_ids.c b/arch/powerpc/cpu/mpc85xx/b4860_ids.c
index 598f7bd..fd7f5fa 100644
--- a/arch/powerpc/cpu/mpc85xx/b4860_ids.c
+++ b/arch/powerpc/cpu/mpc85xx/b4860_ids.c
@@ -57,7 +57,7 @@ struct liodn_id_table liodn_tbl[] = {
 
 	SET_USB_LIODN(1, "fsl-usb2-dr", 553),
 
-	SET_PCI_LIODN(CONFIG_SYS_FSL_PCIE_COMPAT, 1, 148),
+	SET_PCI_LIODN_BASE(CONFIG_SYS_FSL_PCIE_COMPAT, 1, 148),
 
 	SET_DMA_LIODN(1, "fsl,elo3-dma", 147),
 	SET_DMA_LIODN(2, "fsl,elo3-dma", 227),
diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c
index 85d32fc..4cf8853 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c
@@ -424,7 +424,6 @@ void fsl_erratum_a007212_workaround(void)
 
 ulong cpu_init_f(void)
 {
-	ulong flag = 0;
 	extern void m8560_cpm_reset (void);
 #if defined(CONFIG_SYS_DCSRBAR_PHYS) || \
 	(defined(CONFIG_SECURE_BOOT) && defined(CONFIG_FSL_CORENET))
@@ -499,18 +498,11 @@ ulong cpu_init_f(void)
 	in_be32(&gur->dcsrcr);
 #endif
 
-#ifdef CONFIG_SYS_DCSRBAR_PHYS
-#ifdef CONFIG_DEEP_SLEEP
-	/* disable the console if boot from deep sleep */
-	if (in_be32(&gur->scrtsr[0]) & (1 << 3))
-		flag = GD_FLG_SILENT | GD_FLG_DISABLE_CONSOLE;
-#endif
-#endif
 #ifdef CONFIG_SYS_FSL_ERRATUM_A007212
 	fsl_erratum_a007212_workaround();
 #endif
 
-	return flag;
+	return 0;
 }
 
 /* Implement a dummy function for those platforms w/o SERDES */
diff --git a/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c b/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c
index 5cfae47..acb1353 100644
--- a/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c
+++ b/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c
@@ -15,16 +15,16 @@
 #include "fsl_corenet2_serdes.h"
 
 #ifdef CONFIG_SYS_FSL_SRDS_1
-static u64 serdes1_prtcl_map;
+static u8 serdes1_prtcl_map[SERDES_PRCTL_COUNT];
 #endif
 #ifdef CONFIG_SYS_FSL_SRDS_2
-static u64 serdes2_prtcl_map;
+static u8 serdes2_prtcl_map[SERDES_PRCTL_COUNT];
 #endif
 #ifdef CONFIG_SYS_FSL_SRDS_3
-static u64 serdes3_prtcl_map;
+static u8 serdes3_prtcl_map[SERDES_PRCTL_COUNT];
 #endif
 #ifdef CONFIG_SYS_FSL_SRDS_4
-static u64 serdes4_prtcl_map;
+static u8 serdes4_prtcl_map[SERDES_PRCTL_COUNT];
 #endif
 
 #ifdef DEBUG
@@ -78,24 +78,30 @@ static const char *serdes_prtcl_str[] = {
 	[INTERLAKEN] = "INTERLAKEN",
 	[QSGMII_SW1_A] = "QSGMII_SW1_A",
 	[QSGMII_SW1_B] = "QSGMII_SW1_B",
+	[SGMII_SW1_MAC1] = "SGMII_SW1_MAC1",
+	[SGMII_SW1_MAC2] = "SGMII_SW1_MAC2",
+	[SGMII_SW1_MAC3] = "SGMII_SW1_MAC3",
+	[SGMII_SW1_MAC4] = "SGMII_SW1_MAC4",
+	[SGMII_SW1_MAC5] = "SGMII_SW1_MAC5",
+	[SGMII_SW1_MAC6] = "SGMII_SW1_MAC6",
 };
 #endif
 
 int is_serdes_configured(enum srds_prtcl device)
 {
-	u64 ret = 0;
+	int ret = 0;
 
 #ifdef CONFIG_SYS_FSL_SRDS_1
-	ret |= (1ULL << device) & serdes1_prtcl_map;
+	ret |= serdes1_prtcl_map[device];
 #endif
 #ifdef CONFIG_SYS_FSL_SRDS_2
-	ret |= (1ULL << device) & serdes2_prtcl_map;
+	ret |= serdes2_prtcl_map[device];
 #endif
 #ifdef CONFIG_SYS_FSL_SRDS_3
-	ret |= (1ULL << device) & serdes3_prtcl_map;
+	ret |= serdes3_prtcl_map[device];
 #endif
 #ifdef CONFIG_SYS_FSL_SRDS_4
-	ret |= (1ULL << device) & serdes4_prtcl_map;
+	ret |= serdes4_prtcl_map[device];
 #endif
 
 	return !!ret;
@@ -171,12 +177,14 @@ int serdes_get_first_lane(u32 sd, enum srds_prtcl device)
 #define BCAP_OVD_MASK		0x10000000
 #define BYP_CAL_MASK		0x02000000
 
-u64 serdes_init(u32 sd, u32 sd_addr, u32 sd_prctl_mask, u32 sd_prctl_shift)
+void serdes_init(u32 sd, u32 sd_addr, u32 sd_prctl_mask, u32 sd_prctl_shift,
+		u8 serdes_prtcl_map[SERDES_PRCTL_COUNT])
 {
 	ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
-	u64 serdes_prtcl_map = 0;
 	u32 cfg;
 	int lane;
+
+	memset(serdes_prtcl_map, 0, sizeof(serdes_prtcl_map));
 #ifdef CONFIG_SYS_FSL_ERRATUM_A007186
 	struct ccsr_sfp_regs  __iomem *sfp_regs =
 			(struct ccsr_sfp_regs __iomem *)(CONFIG_SYS_SFP_ADDR);
@@ -312,38 +320,43 @@ u64 serdes_init(u32 sd, u32 sd_addr, u32 sd_prctl_mask, u32 sd_prctl_shift)
 
 	for (lane = 0; lane < SRDS_MAX_LANES; lane++) {
 		enum srds_prtcl lane_prtcl = serdes_get_prtcl(sd, cfg, lane);
-		serdes_prtcl_map |= (1ULL << lane_prtcl);
+		if (unlikely(lane_prtcl >= SERDES_PRCTL_COUNT))
+			debug("Unknown SerDes lane protocol %d\n", lane_prtcl);
+		else
+			serdes_prtcl_map[lane_prtcl] = 1;
 	}
-
-	return serdes_prtcl_map;
 }
 
 void fsl_serdes_init(void)
 {
 
 #ifdef CONFIG_SYS_FSL_SRDS_1
-	serdes1_prtcl_map = serdes_init(FSL_SRDS_1,
-		CONFIG_SYS_FSL_CORENET_SERDES_ADDR,
-		FSL_CORENET2_RCWSR4_SRDS1_PRTCL,
-		FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT);
+	serdes_init(FSL_SRDS_1,
+		    CONFIG_SYS_FSL_CORENET_SERDES_ADDR,
+		    FSL_CORENET2_RCWSR4_SRDS1_PRTCL,
+		    FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT,
+		    serdes1_prtcl_map);
 #endif
 #ifdef CONFIG_SYS_FSL_SRDS_2
-	serdes2_prtcl_map = serdes_init(FSL_SRDS_2,
-		CONFIG_SYS_FSL_CORENET_SERDES_ADDR + FSL_SRDS_2 * 0x1000,
-		FSL_CORENET2_RCWSR4_SRDS2_PRTCL,
-		FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT);
+	serdes_init(FSL_SRDS_2,
+		    CONFIG_SYS_FSL_CORENET_SERDES_ADDR + FSL_SRDS_2 * 0x1000,
+		    FSL_CORENET2_RCWSR4_SRDS2_PRTCL,
+		    FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT,
+		    serdes2_prtcl_map);
 #endif
 #ifdef CONFIG_SYS_FSL_SRDS_3
-	serdes3_prtcl_map = serdes_init(FSL_SRDS_3,
-		CONFIG_SYS_FSL_CORENET_SERDES_ADDR + FSL_SRDS_3 * 0x1000,
-		FSL_CORENET2_RCWSR4_SRDS3_PRTCL,
-		FSL_CORENET2_RCWSR4_SRDS3_PRTCL_SHIFT);
+	serdes_init(FSL_SRDS_3,
+		    CONFIG_SYS_FSL_CORENET_SERDES_ADDR + FSL_SRDS_3 * 0x1000,
+		    FSL_CORENET2_RCWSR4_SRDS3_PRTCL,
+		    FSL_CORENET2_RCWSR4_SRDS3_PRTCL_SHIFT,
+		    serdes3_prtcl_map);
 #endif
 #ifdef CONFIG_SYS_FSL_SRDS_4
-	serdes4_prtcl_map = serdes_init(FSL_SRDS_4,
-		CONFIG_SYS_FSL_CORENET_SERDES_ADDR + FSL_SRDS_4 * 0x1000,
-		FSL_CORENET2_RCWSR4_SRDS4_PRTCL,
-		FSL_CORENET2_RCWSR4_SRDS4_PRTCL_SHIFT);
+	serdes_init(FSL_SRDS_4,
+		    CONFIG_SYS_FSL_CORENET_SERDES_ADDR + FSL_SRDS_4 * 0x1000,
+		    FSL_CORENET2_RCWSR4_SRDS4_PRTCL,
+		    FSL_CORENET2_RCWSR4_SRDS4_PRTCL_SHIFT,
+		    serdes4_prtcl_map);
 #endif
 
 }
diff --git a/arch/powerpc/cpu/mpc85xx/t1024_serdes.c b/arch/powerpc/cpu/mpc85xx/t1024_serdes.c
index 7dc8385..2ba314a 100644
--- a/arch/powerpc/cpu/mpc85xx/t1024_serdes.c
+++ b/arch/powerpc/cpu/mpc85xx/t1024_serdes.c
@@ -11,6 +11,7 @@
 
 
 static u8 serdes_cfg_tbl[][4] = {
+	[0x40] = {PCIE1, PCIE1, PCIE1, PCIE1},
 	[0xD5] = {QSGMII_FM1_A, PCIE3, PCIE2, PCIE1},
 	[0xD6] = {QSGMII_FM1_A, PCIE3, PCIE2, SATA1},
 	[0x95] = {XFI_FM1_MAC1, PCIE3, PCIE2, PCIE1},
@@ -20,6 +21,7 @@ static u8 serdes_cfg_tbl[][4] = {
 	[0x56] = {PCIE1, PCIE3, PCIE2, SATA1},
 	[0x5A] = {PCIE1, PCIE3, SGMII_FM1_DTSEC2, SATA1},
 	[0x5B] = {PCIE1, PCIE3, SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC1},
+	[0x5F] = {PCIE1, PCIE3, SGMII_2500_FM1_DTSEC2, SGMII_2500_FM1_DTSEC1},
 	[0x6A] = {PCIE1, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC2, SATA1},
 	[0x6B] = {PCIE1, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC1},
 	[0x6F] = {PCIE1, SGMII_FM1_DTSEC3, SGMII_2500_FM1_DTSEC2,
diff --git a/arch/powerpc/cpu/mpc85xx/t1040_serdes.c b/arch/powerpc/cpu/mpc85xx/t1040_serdes.c
index d86bb27..d5dccd5 100644
--- a/arch/powerpc/cpu/mpc85xx/t1040_serdes.c
+++ b/arch/powerpc/cpu/mpc85xx/t1040_serdes.c
@@ -33,10 +33,10 @@ static u8 serdes_cfg_tbl[][SRDS_MAX_LANES] = {
 		PCIE2, PCIE2, SGMII_FM1_DTSEC4, SGMII_FM1_DTSEC5},
 	[0x87] = {PCIE1, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
 		PCIE2, PCIE3, PCIE4, SGMII_FM1_DTSEC5},
-	[0x89] = {PCIE1, QSGMII_SW1_A, QSGMII_SW1_A, QSGMII_SW1_A,
-		PCIE2, PCIE3, QSGMII_SW1_B, SATA1},
-	[0x8D] = {PCIE1, QSGMII_SW1_A, QSGMII_SW1_A, QSGMII_SW1_A,
-		PCIE2, QSGMII_SW1_B, QSGMII_SW1_B, QSGMII_SW1_B},
+	[0x89] = {PCIE1, SGMII_SW1_MAC3, SGMII_SW1_MAC1, SGMII_SW1_MAC2,
+		PCIE2, PCIE3, SGMII_SW1_MAC4, SATA1},
+	[0x8D] = {PCIE1, SGMII_SW1_MAC3, SGMII_SW1_MAC1, SGMII_SW1_MAC2,
+		PCIE2, SGMII_SW1_MAC6, SGMII_SW1_MAC4, SGMII_SW1_MAC5},
 	[0x8F] = {PCIE1, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
 		AURORA, NONE, SGMII_FM1_DTSEC4, SGMII_FM1_DTSEC5},
 	[0xA5] = {PCIE1, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
diff --git a/arch/powerpc/cpu/mpc8xxx/cpu.c b/arch/powerpc/cpu/mpc8xxx/cpu.c
index 2d28eb2..c92589f 100644
--- a/arch/powerpc/cpu/mpc8xxx/cpu.c
+++ b/arch/powerpc/cpu/mpc8xxx/cpu.c
@@ -15,6 +15,7 @@
 #include <netdev.h>
 #include <asm/cache.h>
 #include <asm/io.h>
+#include <vsc9953.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -271,5 +272,9 @@ int cpu_eth_init(bd_t *bis)
 #ifdef CONFIG_FMAN_ENET
 	fm_standard_init(bis);
 #endif
+
+#ifdef CONFIG_VSC9953
+	vsc9953_init(bis);
+#endif
 	return 0;
 }
diff --git a/arch/powerpc/cpu/mpc8xxx/fdt.c b/arch/powerpc/cpu/mpc8xxx/fdt.c
index 1c63f93..9cc1676 100644
--- a/arch/powerpc/cpu/mpc8xxx/fdt.c
+++ b/arch/powerpc/cpu/mpc8xxx/fdt.c
@@ -73,176 +73,6 @@ void ft_fixup_num_cores(void *blob) {
 }
 #endif /* defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx) */
 
-/*
- * update crypto node properties to a specified revision of the SEC
- * called with sec_rev == 0 if not on an E processor
- */
-#if CONFIG_SYS_FSL_SEC_COMPAT == 2 /* SEC 2.x/3.x */
-void fdt_fixup_crypto_node(void *blob, int sec_rev)
-{
-	static const struct sec_rev_prop {
-		u32 sec_rev;
-		u32 num_channels;
-		u32 channel_fifo_len;
-		u32 exec_units_mask;
-		u32 descriptor_types_mask;
-	} sec_rev_prop_list [] = {
-		{ 0x0200, 4, 24, 0x07e, 0x01010ebf }, /* SEC 2.0 */
-		{ 0x0201, 4, 24, 0x0fe, 0x012b0ebf }, /* SEC 2.1 */
-		{ 0x0202, 1, 24, 0x04c, 0x0122003f }, /* SEC 2.2 */
-		{ 0x0204, 4, 24, 0x07e, 0x012b0ebf }, /* SEC 2.4 */
-		{ 0x0300, 4, 24, 0x9fe, 0x03ab0ebf }, /* SEC 3.0 */
-		{ 0x0301, 4, 24, 0xbfe, 0x03ab0ebf }, /* SEC 3.1 */
-		{ 0x0303, 4, 24, 0x97c, 0x03a30abf }, /* SEC 3.3 */
-	};
-	static char compat_strlist[ARRAY_SIZE(sec_rev_prop_list) *
-				   sizeof("fsl,secX.Y")];
-	int crypto_node, sec_idx, err;
-	char *p;
-	u32 val;
-
-	/* locate crypto node based on lowest common compatible */
-	crypto_node = fdt_node_offset_by_compatible(blob, -1, "fsl,sec2.0");
-	if (crypto_node == -FDT_ERR_NOTFOUND)
-		return;
-
-	/* delete it if not on an E-processor */
-	if (crypto_node > 0 && !sec_rev) {
-		fdt_del_node(blob, crypto_node);
-		return;
-	}
-
-	/* else we got called for possible uprev */
-	for (sec_idx = 0; sec_idx < ARRAY_SIZE(sec_rev_prop_list); sec_idx++)
-		if (sec_rev_prop_list[sec_idx].sec_rev == sec_rev)
-			break;
-
-	if (sec_idx == ARRAY_SIZE(sec_rev_prop_list)) {
-		puts("warning: unknown SEC revision number\n");
-		return;
-	}
-
-	val = cpu_to_fdt32(sec_rev_prop_list[sec_idx].num_channels);
-	err = fdt_setprop(blob, crypto_node, "fsl,num-channels", &val, 4);
-	if (err < 0)
-		printf("WARNING: could not set crypto property: %s\n",
-		       fdt_strerror(err));
-
-	val = cpu_to_fdt32(sec_rev_prop_list[sec_idx].descriptor_types_mask);
-	err = fdt_setprop(blob, crypto_node, "fsl,descriptor-types-mask", &val, 4);
-	if (err < 0)
-		printf("WARNING: could not set crypto property: %s\n",
-		       fdt_strerror(err));
-
-	val = cpu_to_fdt32(sec_rev_prop_list[sec_idx].exec_units_mask);
-	err = fdt_setprop(blob, crypto_node, "fsl,exec-units-mask", &val, 4);
-	if (err < 0)
-		printf("WARNING: could not set crypto property: %s\n",
-		       fdt_strerror(err));
-
-	val = cpu_to_fdt32(sec_rev_prop_list[sec_idx].channel_fifo_len);
-	err = fdt_setprop(blob, crypto_node, "fsl,channel-fifo-len", &val, 4);
-	if (err < 0)
-		printf("WARNING: could not set crypto property: %s\n",
-		       fdt_strerror(err));
-
-	val = 0;
-	while (sec_idx >= 0) {
-		p = compat_strlist + val;
-		val += sprintf(p, "fsl,sec%d.%d",
-			(sec_rev_prop_list[sec_idx].sec_rev & 0xff00) >> 8,
-			sec_rev_prop_list[sec_idx].sec_rev & 0x00ff) + 1;
-		sec_idx--;
-	}
-	err = fdt_setprop(blob, crypto_node, "compatible", &compat_strlist, val);
-	if (err < 0)
-		printf("WARNING: could not set crypto property: %s\n",
-		       fdt_strerror(err));
-}
-#elif CONFIG_SYS_FSL_SEC_COMPAT >= 4  /* SEC4 */
-static u8 caam_get_era(void)
-{
-	static const struct {
-		u16 ip_id;
-		u8 maj_rev;
-		u8 era;
-	} caam_eras[] = {
-		{0x0A10, 1, 1},
-		{0x0A10, 2, 2},
-		{0x0A12, 1, 3},
-		{0x0A14, 1, 3},
-		{0x0A14, 2, 4},
-		{0x0A16, 1, 4},
-		{0x0A10, 3, 4},
-		{0x0A11, 1, 4},
-		{0x0A18, 1, 4},
-		{0x0A11, 2, 5},
-		{0x0A12, 2, 5},
-		{0x0A13, 1, 5},
-		{0x0A1C, 1, 5}
-	};
-
-	ccsr_sec_t __iomem *sec = (void __iomem *)CONFIG_SYS_FSL_SEC_ADDR;
-	u32 secvid_ms = sec_in32(&sec->secvid_ms);
-	u32 ccbvid = sec_in32(&sec->ccbvid);
-	u16 ip_id = (secvid_ms & SEC_SECVID_MS_IPID_MASK) >>
-				SEC_SECVID_MS_IPID_SHIFT;
-	u8 maj_rev = (secvid_ms & SEC_SECVID_MS_MAJ_REV_MASK) >>
-				SEC_SECVID_MS_MAJ_REV_SHIFT;
-	u8 era = (ccbvid & SEC_CCBVID_ERA_MASK) >> SEC_CCBVID_ERA_SHIFT;
-
-	int i;
-
-	if (era)	/* This is '0' prior to CAAM ERA-6 */
-		return era;
-
-	for (i = 0; i < ARRAY_SIZE(caam_eras); i++)
-		if (caam_eras[i].ip_id == ip_id &&
-		    caam_eras[i].maj_rev == maj_rev)
-			return caam_eras[i].era;
-
-	return 0;
-}
-
-static void fdt_fixup_crypto_era(void *blob, u32 era)
-{
-	int err;
-	int crypto_node;
-
-	crypto_node = fdt_path_offset(blob, "crypto");
-	if (crypto_node < 0) {
-		printf("WARNING: Missing crypto node\n");
-		return;
-	}
-
-	err = fdt_setprop(blob, crypto_node, "fsl,sec-era", &era,
-			  sizeof(era));
-	if (err < 0) {
-		printf("ERROR: could not set fsl,sec-era property: %s\n",
-		       fdt_strerror(err));
-	}
-}
-
-void fdt_fixup_crypto_node(void *blob, int sec_rev)
-{
-	u8 era;
-
-	if (!sec_rev) {
-		fdt_del_node_and_alias(blob, "crypto");
-		return;
-	}
-
-	/* Add SEC ERA information in compatible */
-	era = caam_get_era();
-	if (era) {
-		fdt_fixup_crypto_era(blob, era);
-	} else {
-		printf("WARNING: Unable to get ERA for CAAM rev: %d\n",
-			sec_rev);
-	}
-}
-#endif
-
 int fdt_fixup_phy_connection(void *blob, int offset, phy_interface_t phyc)
 {
 	return fdt_setprop_string(blob, offset, "phy-connection-type",
diff --git a/arch/powerpc/cpu/ppc4xx/Kconfig b/arch/powerpc/cpu/ppc4xx/Kconfig
index a40ae3b..5db5e34 100644
--- a/arch/powerpc/cpu/ppc4xx/Kconfig
+++ b/arch/powerpc/cpu/ppc4xx/Kconfig
@@ -101,12 +101,6 @@ config TARGET_FX12MM
 config TARGET_V5FX30TEVAL
 	bool "Support v5fx30teval"
 
-config TARGET_CATCENTER
-	bool "Support CATcenter"
-
-config TARGET_PPCHAMELEONEVB
-	bool "Support PPChameleonEVB"
-
 config TARGET_CPCI2DP
 	bool "Support CPCI2DP"
 
@@ -199,7 +193,6 @@ source "board/avnet/fx12mm/Kconfig"
 source "board/avnet/v5fx30teval/Kconfig"
 source "board/csb272/Kconfig"
 source "board/csb472/Kconfig"
-source "board/dave/PPChameleonEVB/Kconfig"
 source "board/esd/cpci2dp/Kconfig"
 source "board/esd/cpci405/Kconfig"
 source "board/esd/plu405/Kconfig"
diff --git a/arch/powerpc/include/asm/arch-mpc85xx/gpio.h b/arch/powerpc/include/asm/arch-mpc85xx/gpio.h
new file mode 100644
index 0000000..8beed30
--- /dev/null
+++ b/arch/powerpc/include/asm/arch-mpc85xx/gpio.h
@@ -0,0 +1,15 @@
+/*
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * Dummy header file to enable CONFIG_OF_CONTROL.
+ * If CONFIG_OF_CONTROL is enabled, lib/fdtdec.c is compiled.
+ * It includes <asm/arch/gpio.h> via <asm/gpio.h>, so those SoCs that enable
+ * OF_CONTROL must have arch/gpio.h.
+ */
+
+#ifndef __ASM_ARCH_MX85XX_GPIO_H
+#define __ASM_ARCH_MX85XX_GPIO_H
+
+#endif
diff --git a/arch/powerpc/include/asm/config.h b/arch/powerpc/include/asm/config.h
index 423a6fb..65496d0 100644
--- a/arch/powerpc/include/asm/config.h
+++ b/arch/powerpc/include/asm/config.h
@@ -75,6 +75,7 @@
  * SEC (crypto unit) major compatible version determination
  */
 #if defined(CONFIG_MPC83xx)
+#define CONFIG_SYS_FSL_SEC_BE
 #define CONFIG_SYS_FSL_SEC_COMPAT	2
 #endif
 
diff --git a/arch/powerpc/include/asm/fsl_secure_boot.h b/arch/powerpc/include/asm/fsl_secure_boot.h
index 14c6fc3..b4c0c99 100644
--- a/arch/powerpc/include/asm/fsl_secure_boot.h
+++ b/arch/powerpc/include/asm/fsl_secure_boot.h
@@ -12,6 +12,8 @@
 #define CONFIG_SYS_PBI_FLASH_BASE		0xc0000000
 #elif defined(CONFIG_BSC9132QDS)
 #define CONFIG_SYS_PBI_FLASH_BASE		0xc8000000
+#elif defined(CONFIG_C29XPCIE)
+#define CONFIG_SYS_PBI_FLASH_BASE		0xcc000000
 #else
 #define CONFIG_SYS_PBI_FLASH_BASE		0xce000000
 #endif
diff --git a/arch/powerpc/include/asm/fsl_serdes.h b/arch/powerpc/include/asm/fsl_serdes.h
index 8e0e190..45e248e 100644
--- a/arch/powerpc/include/asm/fsl_serdes.h
+++ b/arch/powerpc/include/asm/fsl_serdes.h
@@ -87,6 +87,13 @@ enum srds_prtcl {
 	SGMII_2500_FM2_DTSEC6,
 	SGMII_2500_FM2_DTSEC9,
 	SGMII_2500_FM2_DTSEC10,
+	SGMII_SW1_MAC1,
+	SGMII_SW1_MAC2,
+	SGMII_SW1_MAC3,
+	SGMII_SW1_MAC4,
+	SGMII_SW1_MAC5,
+	SGMII_SW1_MAC6,
+	SERDES_PRCTL_COUNT	/* Keep this item the last one */
 };
 
 enum srds {
diff --git a/arch/powerpc/lib/board.c b/arch/powerpc/lib/board.c
index e6d5355..91645d3 100644
--- a/arch/powerpc/lib/board.c
+++ b/arch/powerpc/lib/board.c
@@ -346,13 +346,6 @@ void board_init_f(ulong bootflag)
 #ifdef CONFIG_PRAM
 	ulong reg;
 #endif
-#ifdef CONFIG_DEEP_SLEEP
-	const ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
-	struct ccsr_scfg *scfg = (void *)CONFIG_SYS_MPC85xx_SCFG;
-	u32 start_addr;
-	typedef void (*func_t)(void);
-	func_t kernel_resume;
-#endif
 
 	/* Pointer is writable since we allocated a register for it */
 	gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET);
@@ -372,20 +365,6 @@ void board_init_f(ulong bootflag)
 		if ((*init_fnc_ptr) () != 0)
 			hang();
 
-#ifdef CONFIG_DEEP_SLEEP
-	/* Jump to kernel in deep sleep case */
-	if (in_be32(&gur->scrtsr[0]) & (1 << 3)) {
-		l2cache_init();
-#if defined(CONFIG_RAMBOOT_PBL)
-		disable_cpc_sram();
-#endif
-		enable_cpc();
-		start_addr = in_be32(&scfg->sparecr[1]);
-		kernel_resume = (func_t)start_addr;
-		kernel_resume();
-	}
-#endif
-
 #ifdef CONFIG_POST
 	post_bootmode_init();
 	post_run(NULL, POST_ROM | post_bootmode_get(NULL));