Merge branch 'u-boot/master' into 'u-boot-arm/master'

14 files changed, 113 insertions, 556 deletions

diff --git a/arch/powerpc/cpu/mpc8260/ether_fcc.c b/arch/powerpc/cpu/mpc8260/ether_fcc.c
index f9f15b5..30ea3de 100644
--- a/arch/powerpc/cpu/mpc8260/ether_fcc.c
+++ b/arch/powerpc/cpu/mpc8260/ether_fcc.c
@@ -183,7 +183,7 @@ static int fec_recv(struct eth_device* dev)
 	}
 	else {
 	    /* Pass the packet up to the protocol layers. */
-	    NetReceive(NetRxPackets[rxIdx], length - 4);
+	    net_process_received_packet(net_rx_packets[rxIdx], length - 4);
 	}
 
 
@@ -243,7 +243,7 @@ static int fec_init(struct eth_device* dev, bd_t *bis)
     {
       rtx.rxbd[i].cbd_sc = BD_ENET_RX_EMPTY;
       rtx.rxbd[i].cbd_datlen = 0;
-      rtx.rxbd[i].cbd_bufaddr = (uint)NetRxPackets[i];
+      rtx.rxbd[i].cbd_bufaddr = (uint)net_rx_packets[i];
     }
     rtx.rxbd[PKTBUFSRX - 1].cbd_sc |= BD_ENET_RX_WRAP;
 
@@ -299,7 +299,7 @@ static int fec_init(struct eth_device* dev, bd_t *bis)
      * it unique by setting a few bits in the upper byte of the
      * non-static part of the address.
      */
-#define ea eth_get_dev()->enetaddr
+#define ea eth_get_ethaddr()
     pram_ptr->fen_paddrh = (ea[5] << 8) + ea[4];
     pram_ptr->fen_paddrm = (ea[3] << 8) + ea[2];
     pram_ptr->fen_paddrl = (ea[1] << 8) + ea[0];
@@ -637,7 +637,7 @@ eth_loopback_test (void)
 
 	puts ("FCC Ethernet External loopback test\n");
 
-	eth_getenv_enetaddr("ethaddr", NetOurEther);
+	eth_getenv_enetaddr("ethaddr", net_ethaddr);
 
 	/*
 	 * global initialisations for all FCC channels
@@ -720,8 +720,8 @@ eth_loopback_test (void)
 			bdp->cbd_sc = BD_ENET_TX_READY | BD_ENET_TX_PAD | \
 				BD_ENET_TX_LAST | BD_ENET_TX_TC;
 
-			memset ((void *)bp, patbytes[i], ELBT_BUFSZ);
-			NetSetEther (bp, NetBcastAddr, 0x8000);
+			memset((void *)bp, patbytes[i], ELBT_BUFSZ);
+			net_set_ether(bp, net_bcast_ethaddr, 0x8000);
 		}
 		ecp->txbd[ELBT_NTXBD - 1].cbd_sc |= BD_ENET_TX_WRAP;
 
@@ -799,11 +799,9 @@ eth_loopback_test (void)
 		 * So, far we have only been given one Ethernet address. We use
 		 * the same address for all channels
 		 */
-#define ea NetOurEther
-		fpp->fen_paddrh = (ea[5] << 8) + ea[4];
-		fpp->fen_paddrm = (ea[3] << 8) + ea[2];
-		fpp->fen_paddrl = (ea[1] << 8) + ea[0];
-#undef ea
+		fpp->fen_paddrh = (net_ethaddr[5] << 8) + net_ethaddr[4];
+		fpp->fen_paddrm = (net_ethaddr[3] << 8) + net_ethaddr[2];
+		fpp->fen_paddrl = (net_ethaddr[1] << 8) + net_ethaddr[0];
 
 		fpp->fen_minflr = PKT_MINBUF_SIZE; /* min frame len register */
 		/*
@@ -1016,7 +1014,7 @@ eth_loopback_test (void)
 							&ecp->rxbufs[i][0];
 
 						ours = memcmp (ehp->et_src, \
-							NetOurEther, 6);
+							net_ethaddr, 6);
 
 						prot = swap16 (ehp->et_protlen);
 						tb = prot & 0x8000;
diff --git a/arch/powerpc/cpu/mpc8260/ether_scc.c b/arch/powerpc/cpu/mpc8260/ether_scc.c
index c988def..5ba8bed 100644
--- a/arch/powerpc/cpu/mpc8260/ether_scc.c
+++ b/arch/powerpc/cpu/mpc8260/ether_scc.c
@@ -146,7 +146,7 @@ static int sec_rx(struct eth_device *dev)
 	else
 	{
 	    /* Pass the packet up to the protocol layers. */
-	    NetReceive(NetRxPackets[rxIdx], length - 4);
+	    net_process_received_packet(net_rx_packets[rxIdx], length - 4);
 	}
 
 
@@ -263,7 +263,7 @@ static int sec_init(struct eth_device *dev, bd_t *bis)
     {
 	rtx->rxbd[i].cbd_sc = BD_ENET_RX_EMPTY;
 	rtx->rxbd[i].cbd_datlen = 0;                  /* Reset */
-	rtx->rxbd[i].cbd_bufaddr = (uint)NetRxPackets[i];
+	rtx->rxbd[i].cbd_bufaddr = (uint)net_rx_packets[i];
     }
 
     rtx->rxbd[PKTBUFSRX - 1].cbd_sc |= BD_ENET_RX_WRAP;
diff --git a/arch/powerpc/cpu/mpc83xx/Kconfig b/arch/powerpc/cpu/mpc83xx/Kconfig
index 4d6cb09..88a3bd6 100644
--- a/arch/powerpc/cpu/mpc83xx/Kconfig
+++ b/arch/powerpc/cpu/mpc83xx/Kconfig
@@ -49,6 +49,7 @@ config TARGET_MPC837XERDB
 
 config TARGET_IDS8313
 	bool "Support ids8313"
+	select DM
 
 config TARGET_KM8360
 	bool "Support km8360"
diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init_early.c b/arch/powerpc/cpu/mpc85xx/cpu_init_early.c
index 5ca9bf5..235a635 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu_init_early.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu_init_early.c
@@ -15,7 +15,7 @@ DECLARE_GLOBAL_DATA_PTR;
 #ifdef CONFIG_A003399_NOR_WORKAROUND
 void setup_ifc(void)
 {
-	struct fsl_ifc *ifc_regs = (void *)CONFIG_SYS_IFC_ADDR;
+	struct fsl_ifc ifc_regs = {(void *)CONFIG_SYS_IFC_ADDR, (void *)NULL};
 	u32 _mas0, _mas1, _mas2, _mas3, _mas7;
 	phys_addr_t flash_phys = CONFIG_SYS_FLASH_BASE_PHYS;
 
@@ -70,9 +70,9 @@ void setup_ifc(void)
 #endif
 
 	/* Change flash's physical address */
-	ifc_out32(&(ifc_regs->cspr_cs[0].cspr), CONFIG_SYS_CSPR0);
-	ifc_out32(&(ifc_regs->csor_cs[0].csor), CONFIG_SYS_CSOR0);
-	ifc_out32(&(ifc_regs->amask_cs[0].amask), CONFIG_SYS_AMASK0);
+	ifc_out32(&(ifc_regs.gregs->cspr_cs[0].cspr), CONFIG_SYS_CSPR0);
+	ifc_out32(&(ifc_regs.gregs->csor_cs[0].csor), CONFIG_SYS_CSOR0);
+	ifc_out32(&(ifc_regs.gregs->amask_cs[0].amask), CONFIG_SYS_AMASK0);
 
 	return ;
 }
diff --git a/arch/powerpc/cpu/mpc85xx/ether_fcc.c b/arch/powerpc/cpu/mpc85xx/ether_fcc.c
index 166dc9e..14358ae 100644
--- a/arch/powerpc/cpu/mpc85xx/ether_fcc.c
+++ b/arch/powerpc/cpu/mpc85xx/ether_fcc.c
@@ -186,7 +186,7 @@ static int fec_recv(struct eth_device* dev)
 	}
 	else {
 	    /* Pass the packet up to the protocol layers. */
-	    NetReceive(NetRxPackets[rxIdx], length - 4);
+	    net_process_received_packet(net_rx_packets[rxIdx], length - 4);
 	}
 
 
@@ -263,7 +263,7 @@ static int fec_init(struct eth_device* dev, bd_t *bis)
     {
       rtx.rxbd[i].cbd_sc = BD_ENET_RX_EMPTY;
       rtx.rxbd[i].cbd_datlen = 0;
-      rtx.rxbd[i].cbd_bufaddr = (uint)NetRxPackets[i];
+      rtx.rxbd[i].cbd_bufaddr = (uint)net_rx_packets[i];
     }
     rtx.rxbd[PKTBUFSRX - 1].cbd_sc |= BD_ENET_RX_WRAP;
 
@@ -338,7 +338,7 @@ static int fec_init(struct eth_device* dev, bd_t *bis)
      * it unique by setting a few bits in the upper byte of the
      * non-static part of the address.
      */
-#define ea eth_get_dev()->enetaddr
+#define ea eth_get_ethaddr()
     pram_ptr->fen_paddrh = (ea[5] << 8) + ea[4];
     pram_ptr->fen_paddrm = (ea[3] << 8) + ea[2];
     pram_ptr->fen_paddrl = (ea[1] << 8) + ea[0];
diff --git a/arch/powerpc/cpu/mpc85xx/speed.c b/arch/powerpc/cpu/mpc85xx/speed.c
index e24b857..321ade2 100644
--- a/arch/powerpc/cpu/mpc85xx/speed.c
+++ b/arch/powerpc/cpu/mpc85xx/speed.c
@@ -28,7 +28,7 @@ void get_sys_info(sys_info_t *sys_info)
 {
 	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 #ifdef CONFIG_FSL_IFC
-	struct fsl_ifc *ifc_regs = (void *)CONFIG_SYS_IFC_ADDR;
+	struct fsl_ifc ifc_regs = {(void *)CONFIG_SYS_IFC_ADDR, (void *)NULL};
 	u32 ccr;
 #endif
 #ifdef CONFIG_FSL_CORENET
@@ -597,7 +597,7 @@ void get_sys_info(sys_info_t *sys_info)
 #endif
 
 #if defined(CONFIG_FSL_IFC)
-	ccr = ifc_in32(&ifc_regs->ifc_ccr);
+	ccr = ifc_in32(&ifc_regs.gregs->ifc_ccr);
 	ccr = ((ccr & IFC_CCR_CLK_DIV_MASK) >> IFC_CCR_CLK_DIV_SHIFT) + 1;
 
 	sys_info->freq_localbus = sys_info->freq_systembus / ccr;
diff --git a/arch/powerpc/cpu/mpc85xx/start.S b/arch/powerpc/cpu/mpc85xx/start.S
index d8c9fb6..28f04ee 100644
--- a/arch/powerpc/cpu/mpc85xx/start.S
+++ b/arch/powerpc/cpu/mpc85xx/start.S
@@ -252,39 +252,36 @@ l2_disabled:
 	lis	r1,CONFIG_SYS_MONITOR_BASE@h
 	mtspr	IVPR,r1
 
-	lis	r3,(CONFIG_SYS_MONITOR_BASE & 0xffff)@h
-	ori	r3,r3,(CONFIG_SYS_MONITOR_BASE & 0xffff)@l
-
-	addi	r4,r3,CriticalInput - _start + _START_OFFSET
+	li	r4,CriticalInput@l
 	mtspr	IVOR0,r4	/* 0: Critical input */
-	addi	r4,r3,MachineCheck - _start + _START_OFFSET
+	li	r4,MachineCheck@l
 	mtspr	IVOR1,r4	/* 1: Machine check */
-	addi	r4,r3,DataStorage - _start + _START_OFFSET
+	li	r4,DataStorage@l
 	mtspr	IVOR2,r4	/* 2: Data storage */
-	addi	r4,r3,InstStorage - _start + _START_OFFSET
+	li	r4,InstStorage@l
 	mtspr	IVOR3,r4	/* 3: Instruction storage */
-	addi	r4,r3,ExtInterrupt - _start + _START_OFFSET
+	li	r4,ExtInterrupt@l
 	mtspr	IVOR4,r4	/* 4: External interrupt */
-	addi	r4,r3,Alignment - _start + _START_OFFSET
+	li	r4,Alignment@l
 	mtspr	IVOR5,r4	/* 5: Alignment */
-	addi	r4,r3,ProgramCheck - _start + _START_OFFSET
+	li	r4,ProgramCheck@l
 	mtspr	IVOR6,r4	/* 6: Program check */
-	addi	r4,r3,FPUnavailable - _start + _START_OFFSET
+	li	r4,FPUnavailable@l
 	mtspr	IVOR7,r4	/* 7: floating point unavailable */
-	addi	r4,r3,SystemCall - _start + _START_OFFSET
+	li	r4,SystemCall@l
 	mtspr	IVOR8,r4	/* 8: System call */
 	/* 9: Auxiliary processor unavailable(unsupported) */
-	addi	r4,r3,Decrementer - _start + _START_OFFSET
+	li	r4,Decrementer@l
 	mtspr	IVOR10,r4	/* 10: Decrementer */
-	addi	r4,r3,IntervalTimer - _start + _START_OFFSET
+	li	r4,IntervalTimer@l
 	mtspr	IVOR11,r4	/* 11: Interval timer */
-	addi	r4,r3,WatchdogTimer - _start + _START_OFFSET
+	li	r4,WatchdogTimer@l
 	mtspr	IVOR12,r4	/* 12: Watchdog timer */
-	addi	r4,r3,DataTLBError - _start + _START_OFFSET
+	li	r4,DataTLBError@l
 	mtspr	IVOR13,r4	/* 13: Data TLB error */
-	addi	r4,r3,InstructionTLBError - _start + _START_OFFSET
+	li	r4,InstructionTLBError@l
 	mtspr	IVOR14,r4	/* 14: Instruction TLB error */
-	addi	r4,r3,DebugBreakpoint - _start + _START_OFFSET
+	li	r4,DebugBreakpoint@l
 	mtspr	IVOR15,r4	/* 15: Debug */
 #endif
 
@@ -1121,7 +1118,7 @@ switch_as:
 	/*--------------------------------------------------------------*/
 	lis	r3,CONFIG_SYS_MONITOR_BASE@h
 	ori	r3,r3,CONFIG_SYS_MONITOR_BASE@l
-	addi	r3,r3,_start_cont - _start + _START_OFFSET
+	addi	r3,r3,_start_cont - _start
 	mtlr	r3
 	blr
 #endif
@@ -1165,7 +1162,6 @@ _start_cont:
 	/* NOTREACHED - board_init_f() does not return */
 
 #ifndef MINIMAL_SPL
-	. = EXC_OFF_SYS_RESET
 	.globl	_start_of_vectors
 _start_of_vectors:
 
@@ -1185,7 +1181,6 @@ _start_of_vectors:
 	STD_EXCEPTION(0x0500, ExtInterrupt, ExtIntException)
 
 /* Alignment exception. */
-	. = 0x0600
 Alignment:
 	EXCEPTION_PROLOG(SRR0, SRR1)
 	mfspr	r4,DAR
@@ -1193,87 +1188,20 @@ Alignment:
 	mfspr	r5,DSISR
 	stw	r5,_DSISR(r21)
 	addi	r3,r1,STACK_FRAME_OVERHEAD
-	EXC_XFER_TEMPLATE(Alignment, AlignmentException, MSR_KERNEL, COPY_EE)
+	EXC_XFER_TEMPLATE(0x600, Alignment, AlignmentException,
+		MSR_KERNEL, COPY_EE)
 
 /* Program check exception */
-	. = 0x0700
 ProgramCheck:
 	EXCEPTION_PROLOG(SRR0, SRR1)
 	addi	r3,r1,STACK_FRAME_OVERHEAD
-	EXC_XFER_TEMPLATE(ProgramCheck, ProgramCheckException,
+	EXC_XFER_TEMPLATE(0x700, ProgramCheck, ProgramCheckException,
 		MSR_KERNEL, COPY_EE)
 
 	/* No FPU on MPC85xx.  This exception is not supposed to happen.
 	*/
 	STD_EXCEPTION(0x0800, FPUnavailable, UnknownException)
-
-	. = 0x0900
-/*
- * r0 - SYSCALL number
- * r3-... arguments
- */
-SystemCall:
-	addis	r11,r0,0	/* get functions table addr */
-	ori	r11,r11,0	/* Note: this code is patched in trap_init */
-	addis	r12,r0,0	/* get number of functions */
-	ori	r12,r12,0
-
-	cmplw	0,r0,r12
-	bge	1f
-
-	rlwinm	r0,r0,2,0,31	/* fn_addr = fn_tbl[r0] */
-	add	r11,r11,r0
-	lwz	r11,0(r11)
-
-	li	r20,0xd00-4	/* Get stack pointer */
-	lwz	r12,0(r20)
-	subi	r12,r12,12	/* Adjust stack pointer */
-	li	r0,0xc00+_end_back-SystemCall
-	cmplw	0,r0,r12	/* Check stack overflow */
-	bgt	1f
-	stw	r12,0(r20)
-
-	mflr	r0
-	stw	r0,0(r12)
-	mfspr	r0,SRR0
-	stw	r0,4(r12)
-	mfspr	r0,SRR1
-	stw	r0,8(r12)
-
-	li	r12,0xc00+_back-SystemCall
-	mtlr	r12
-	mtspr	SRR0,r11
-
-1:	SYNC
-	rfi
-_back:
-
-	mfmsr	r11			/* Disable interrupts */
-	li	r12,0
-	ori	r12,r12,MSR_EE
-	andc	r11,r11,r12
-	SYNC				/* Some chip revs need this... */
-	mtmsr	r11
-	SYNC
-
-	li	r12,0xd00-4		/* restore regs */
-	lwz	r12,0(r12)
-
-	lwz	r11,0(r12)
-	mtlr	r11
-	lwz	r11,4(r12)
-	mtspr	SRR0,r11
-	lwz	r11,8(r12)
-	mtspr	SRR1,r11
-
-	addi	r12,r12,12		/* Adjust stack pointer */
-	li	r20,0xd00-4
-	stw	r12,0(r20)
-
-	SYNC
-	rfi
-_end_back:
-
+	STD_EXCEPTION(0x0900, SystemCall, UnknownException)
 	STD_EXCEPTION(0x0a00, Decrementer, timer_interrupt)
 	STD_EXCEPTION(0x0b00, IntervalTimer, UnknownException)
 	STD_EXCEPTION(0x0c00, WatchdogTimer, UnknownException)
@@ -1293,32 +1221,22 @@ _end_of_vectors:
  * This code finishes saving the registers to the exception frame
  * and jumps to the appropriate handler for the exception.
  * Register r21 is pointer into trap frame, r1 has new stack pointer.
+ * r23 is the address of the handler.
  */
 	.globl	transfer_to_handler
 transfer_to_handler:
-	stw	r22,_NIP(r21)
-	lis	r22,MSR_POW@h
-	andc	r23,r23,r22
-	stw	r23,_MSR(r21)
 	SAVE_GPR(7, r21)
 	SAVE_4GPRS(8, r21)
 	SAVE_8GPRS(12, r21)
 	SAVE_8GPRS(24, r21)
 
-	mflr	r23
-	andi.	r24,r23,0x3f00		/* get vector offset */
-	stw	r24,TRAP(r21)
 	li	r22,0
 	stw	r22,RESULT(r21)
 	mtspr	SPRG2,r22		/* r1 is now kernel sp */
 
-	lwz	r24,0(r23)		/* virtual address of handler */
-	lwz	r23,4(r23)		/* where to go when done */
-	mtspr	SRR0,r24
-	mtspr	SRR1,r20
-	mtlr	r23
-	SYNC
-	rfi				/* jump to handler, enable MMU */
+	mtctr	r23			/* virtual address of handler */
+	mtmsr	r20
+	bctrl
 
 int_return:
 	mfmsr	r28		/* Disable interrupts */
@@ -1350,66 +1268,6 @@ int_return:
 	SYNC
 	rfi
 
-crit_return:
-	mfmsr	r28		/* Disable interrupts */
-	li	r4,0
-	ori	r4,r4,MSR_EE
-	andc	r28,r28,r4
-	SYNC			/* Some chip revs need this... */
-	mtmsr	r28
-	SYNC
-	lwz	r2,_CTR(r1)
-	lwz	r0,_LINK(r1)
-	mtctr	r2
-	mtlr	r0
-	lwz	r2,_XER(r1)
-	lwz	r0,_CCR(r1)
-	mtspr	XER,r2
-	mtcrf	0xFF,r0
-	REST_10GPRS(3, r1)
-	REST_10GPRS(13, r1)
-	REST_8GPRS(23, r1)
-	REST_GPR(31, r1)
-	lwz	r2,_NIP(r1)	/* Restore environment */
-	lwz	r0,_MSR(r1)
-	mtspr	SPRN_CSRR0,r2
-	mtspr	SPRN_CSRR1,r0
-	lwz	r0,GPR0(r1)
-	lwz	r2,GPR2(r1)
-	lwz	r1,GPR1(r1)
-	SYNC
-	rfci
-
-mck_return:
-	mfmsr	r28		/* Disable interrupts */
-	li	r4,0
-	ori	r4,r4,MSR_EE
-	andc	r28,r28,r4
-	SYNC			/* Some chip revs need this... */
-	mtmsr	r28
-	SYNC
-	lwz	r2,_CTR(r1)
-	lwz	r0,_LINK(r1)
-	mtctr	r2
-	mtlr	r0
-	lwz	r2,_XER(r1)
-	lwz	r0,_CCR(r1)
-	mtspr	XER,r2
-	mtcrf	0xFF,r0
-	REST_10GPRS(3, r1)
-	REST_10GPRS(13, r1)
-	REST_8GPRS(23, r1)
-	REST_GPR(31, r1)
-	lwz	r2,_NIP(r1)	/* Restore environment */
-	lwz	r0,_MSR(r1)
-	mtspr	SPRN_MCSRR0,r2
-	mtspr	SPRN_MCSRR1,r0
-	lwz	r0,GPR0(r1)
-	lwz	r2,GPR2(r1)
-	lwz	r1,GPR1(r1)
-	SYNC
-	rfmci
-
 /* Cache functions.
 */
 .globl flush_icache
@@ -1494,11 +1352,6 @@ dcache_status:
 	andi.	r3,r3,L1CSR0_DCE
 	blr
 
-	.globl get_pir
-get_pir:
-	mfspr	r3,PIR
-	blr
-
 	.globl get_pvr
 get_pvr:
 	mfspr	r3,PVR
@@ -1509,11 +1362,6 @@ get_svr:
 	mfspr	r3,SVR
 	blr
 
-	.globl wr_tcr
-wr_tcr:
-	mtspr	TCR,r3
-	blr
-
 /*------------------------------------------------------------------------------- */
 /* Function:	 in8 */
 /* Description:	 Input 8 bits */
@@ -1728,7 +1576,7 @@ relocate_code:
  * initialization, now running from RAM.
  */
 
-	addi	r0,r10,in_ram - _start + _START_OFFSET
+	addi	r0,r10,in_ram - _start
 
 	/*
 	 * As IVPR is going to point RAM address,
@@ -1816,89 +1664,41 @@ clear_bss:
 	 */
 	.globl	trap_init
 trap_init:
-	mflr	r4			/* save link register		*/
-	GET_GOT
-	lwz	r7,GOT(_start_of_vectors)
-	lwz	r8,GOT(_end_of_vectors)
-
-	li	r9,0x100		/* reset vector always at 0x100 */
-
-	cmplw	0,r7,r8
-	bgelr				/* return if r7>=r8 - just in case */
-1:
-	lwz	r0,0(r7)
-	stw	r0,0(r9)
-	addi	r7,r7,4
-	addi	r9,r9,4
-	cmplw	0,r7,r8
-	bne	1b
+	/* Update IVORs as per relocation */
+	mtspr	IVPR,r3
 
-	/*
-	 * relocate `hdlr' and `int_return' entries
-	 */
-	li	r7,.L_CriticalInput - _start + _START_OFFSET
-	bl	trap_reloc
-	li	r7,.L_MachineCheck - _start + _START_OFFSET
-	bl	trap_reloc
-	li	r7,.L_DataStorage - _start + _START_OFFSET
-	bl	trap_reloc
-	li	r7,.L_InstStorage - _start + _START_OFFSET
-	bl	trap_reloc
-	li	r7,.L_ExtInterrupt - _start + _START_OFFSET
-	bl	trap_reloc
-	li	r7,.L_Alignment - _start + _START_OFFSET
-	bl	trap_reloc
-	li	r7,.L_ProgramCheck - _start + _START_OFFSET
-	bl	trap_reloc
-	li	r7,.L_FPUnavailable - _start + _START_OFFSET
-	bl	trap_reloc
-	li	r7,.L_Decrementer - _start + _START_OFFSET
-	bl	trap_reloc
-	li	r7,.L_IntervalTimer - _start + _START_OFFSET
-	li	r8,_end_of_vectors - _start + _START_OFFSET
-2:
-	bl	trap_reloc
-	addi	r7,r7,0x100		/* next exception vector	*/
-	cmplw	0,r7,r8
-	blt	2b
-
-	/* Update IVORs as per relocated vector table address */
-	li	r7,0x0100
-	mtspr	IVOR0,r7	/* 0: Critical input */
-	li	r7,0x0200
-	mtspr	IVOR1,r7	/* 1: Machine check */
-	li	r7,0x0300
-	mtspr	IVOR2,r7	/* 2: Data storage */
-	li	r7,0x0400
-	mtspr	IVOR3,r7	/* 3: Instruction storage */
-	li	r7,0x0500
-	mtspr	IVOR4,r7	/* 4: External interrupt */
-	li	r7,0x0600
-	mtspr	IVOR5,r7	/* 5: Alignment */
-	li	r7,0x0700
-	mtspr	IVOR6,r7	/* 6: Program check */
-	li	r7,0x0800
-	mtspr	IVOR7,r7	/* 7: floating point unavailable */
-	li	r7,0x0900
-	mtspr	IVOR8,r7	/* 8: System call */
+	li	r4,CriticalInput@l
+	mtspr	IVOR0,r4	/* 0: Critical input */
+	li	r4,MachineCheck@l
+	mtspr	IVOR1,r4	/* 1: Machine check */
+	li	r4,DataStorage@l
+	mtspr	IVOR2,r4	/* 2: Data storage */
+	li	r4,InstStorage@l
+	mtspr	IVOR3,r4	/* 3: Instruction storage */
+	li	r4,ExtInterrupt@l
+	mtspr	IVOR4,r4	/* 4: External interrupt */
+	li	r4,Alignment@l
+	mtspr	IVOR5,r4	/* 5: Alignment */
+	li	r4,ProgramCheck@l
+	mtspr	IVOR6,r4	/* 6: Program check */
+	li	r4,FPUnavailable@l
+	mtspr	IVOR7,r4	/* 7: floating point unavailable */
+	li	r4,SystemCall@l
+	mtspr	IVOR8,r4	/* 8: System call */
 	/* 9: Auxiliary processor unavailable(unsupported) */
-	li	r7,0x0a00
-	mtspr	IVOR10,r7	/* 10: Decrementer */
-	li	r7,0x0b00
-	mtspr	IVOR11,r7	/* 11: Interval timer */
-	li	r7,0x0c00
-	mtspr	IVOR12,r7	/* 12: Watchdog timer */
-	li	r7,0x0d00
-	mtspr	IVOR13,r7	/* 13: Data TLB error */
-	li	r7,0x0e00
-	mtspr	IVOR14,r7	/* 14: Instruction TLB error */
-	li	r7,0x0f00
-	mtspr	IVOR15,r7	/* 15: Debug */
-
-	lis	r7,0x0
-	mtspr	IVPR,r7
-
-	mtlr	r4			/* restore link register	*/
+	li	r4,Decrementer@l
+	mtspr	IVOR10,r4	/* 10: Decrementer */
+	li	r4,IntervalTimer@l
+	mtspr	IVOR11,r4	/* 11: Interval timer */
+	li	r4,WatchdogTimer@l
+	mtspr	IVOR12,r4	/* 12: Watchdog timer */
+	li	r4,DataTLBError@l
+	mtspr	IVOR13,r4	/* 13: Data TLB error */
+	li	r4,InstructionTLBError@l
+	mtspr	IVOR14,r4	/* 14: Instruction TLB error */
+	li	r4,DebugBreakpoint@l
+	mtspr	IVOR15,r4	/* 15: Debug */
+
 	blr
 
 .globl unlock_ram_in_cache
diff --git a/arch/powerpc/cpu/mpc8xx/fec.c b/arch/powerpc/cpu/mpc8xx/fec.c
index 22b8ec7..2e19603 100644
--- a/arch/powerpc/cpu/mpc8xx/fec.c
+++ b/arch/powerpc/cpu/mpc8xx/fec.c
@@ -247,21 +247,21 @@ static int fec_recv (struct eth_device *dev)
 				rtx->rxbd[rxIdx].cbd_sc);
 #endif
 		} else {
-			uchar *rx = NetRxPackets[rxIdx];
+			uchar *rx = net_rx_packets[rxIdx];
 
 			length -= 4;
 
 #if defined(CONFIG_CMD_CDP)
-			if ((rx[0] & 1) != 0
-			    && memcmp ((uchar *) rx, NetBcastAddr, 6) != 0
-			    && !is_cdp_packet((uchar *)rx))
+			if ((rx[0] & 1) != 0 &&
+			    memcmp((uchar *)rx, net_bcast_ethaddr, 6) != 0 &&
+			    !is_cdp_packet((uchar *)rx))
 				rx = NULL;
 #endif
 			/*
 			 * Pass the packet up to the protocol layers.
 			 */
 			if (rx != NULL)
-				NetReceive (rx, length);
+				net_process_received_packet(rx, length);
 		}
 
 		/* Give the buffer back to the FEC. */
@@ -576,7 +576,7 @@ static int fec_init (struct eth_device *dev, bd_t * bd)
 	for (i = 0; i < PKTBUFSRX; i++) {
 		rtx->rxbd[i].cbd_sc = BD_ENET_RX_EMPTY;
 		rtx->rxbd[i].cbd_datlen = 0;	/* Reset */
-		rtx->rxbd[i].cbd_bufaddr = (uint) NetRxPackets[i];
+		rtx->rxbd[i].cbd_bufaddr = (uint) net_rx_packets[i];
 	}
 	rtx->rxbd[PKTBUFSRX - 1].cbd_sc |= BD_ENET_RX_WRAP;
 
diff --git a/arch/powerpc/cpu/mpc8xx/scc.c b/arch/powerpc/cpu/mpc8xx/scc.c
index 251966b..5498440 100644
--- a/arch/powerpc/cpu/mpc8xx/scc.c
+++ b/arch/powerpc/cpu/mpc8xx/scc.c
@@ -159,7 +159,8 @@ static int scc_recv (struct eth_device *dev)
 #endif
 		} else {
 			/* Pass the packet up to the protocol layers. */
-			NetReceive (NetRxPackets[rxIdx], length - 4);
+			net_process_received_packet(net_rx_packets[rxIdx],
+						    length - 4);
 		}
 
 
@@ -280,7 +281,7 @@ static int scc_init (struct eth_device *dev, bd_t * bis)
 	for (i = 0; i < PKTBUFSRX; i++) {
 		rtx->rxbd[i].cbd_sc = BD_ENET_RX_EMPTY;
 		rtx->rxbd[i].cbd_datlen = 0;	/* Reset */
-		rtx->rxbd[i].cbd_bufaddr = (uint) NetRxPackets[i];
+		rtx->rxbd[i].cbd_bufaddr = (uint) net_rx_packets[i];
 	}
 
 	rtx->rxbd[PKTBUFSRX - 1].cbd_sc |= BD_ENET_RX_WRAP;
@@ -339,7 +340,7 @@ static int scc_init (struct eth_device *dev, bd_t * bis)
 	pram_ptr->sen_gaddr3 = 0x0;	/* Group Address Filter 3 (unused) */
 	pram_ptr->sen_gaddr4 = 0x0;	/* Group Address Filter 4 (unused) */
 
-#define ea eth_get_dev()->enetaddr
+#define ea eth_get_ethaddr()
 	pram_ptr->sen_paddrh = (ea[5] << 8) + ea[4];
 	pram_ptr->sen_paddrm = (ea[3] << 8) + ea[2];
 	pram_ptr->sen_paddrl = (ea[1] << 8) + ea[0];
diff --git a/arch/powerpc/cpu/ppc4xx/Kconfig b/arch/powerpc/cpu/ppc4xx/Kconfig
index 9e52d3f..89cb3e9 100644
--- a/arch/powerpc/cpu/ppc4xx/Kconfig
+++ b/arch/powerpc/cpu/ppc4xx/Kconfig
@@ -43,6 +43,8 @@ config TARGET_BUBINGA
 
 config TARGET_CANYONLANDS
 	bool "Support canyonlands"
+	select DM
+	select DM_SERIAL
 
 config TARGET_EBONY
 	bool "Support ebony"
diff --git a/arch/powerpc/include/asm/fsl_errata.h b/arch/powerpc/include/asm/fsl_errata.h
index 61c6d70..4861e3bf 100644
--- a/arch/powerpc/include/asm/fsl_errata.h
+++ b/arch/powerpc/include/asm/fsl_errata.h
@@ -45,7 +45,7 @@ static inline bool has_erratum_a007186(void)
 		return IS_SVR_REV(svr, 2, 0);
 	case SVR_T2081:
 	case SVR_T2080:
-		return IS_SVR_REV(svr, 1, 0);
+		return IS_SVR_REV(svr, 1, 0) || IS_SVR_REV(svr, 1, 1);
 	}
 
 	return false;
diff --git a/arch/powerpc/include/asm/fsl_memac.h b/arch/powerpc/include/asm/fsl_memac.h
deleted file mode 100644
index bed2a40..0000000
--- a/arch/powerpc/include/asm/fsl_memac.h
+++ /dev/null
@@ -1,264 +0,0 @@
-/*
- * Copyright 2012 Freescale Semiconductor, Inc.
- *	Roy Zang <tie-fei.zang@freescale.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef __MEMAC_H__
-#define __MEMAC_H__
-
-#include <phy.h>
-
-struct memac {
-	/* memac general control and status registers */
-	u32	res_0[2];
-	u32	command_config;	/* Control and configuration register */
-	u32	mac_addr_0;	/* Lower 32 bits of 48-bit MAC address */
-	u32	mac_addr_1;	/* Upper 16 bits of 48-bit MAC address */
-	u32	maxfrm;		/* Maximum frame length register */
-	u32	res_18[5];
-	u32	hashtable_ctrl;	/* Hash table control register */
-	u32	res_30[4];
-	u32	ievent;		/* Interrupt event register */
-	u32	tx_ipg_length;	/* Transmitter inter-packet-gap register */
-	u32	res_48;
-	u32	imask;		/* interrupt mask register */
-	u32	res_50;
-	u32	cl_pause_quanta[4]; /* CL01-CL67 pause quanta register */
-	u32	cl_pause_thresh[4]; /* CL01-CL67 pause thresh register */
-	u32	rx_pause_status;	/* Receive pause status register */
-	u32	res_78[2];
-	u32	mac_addr[14];	/* MAC address */
-	u32	lpwake_timer;	/* EEE low power wakeup timer register */
-	u32	sleep_timer;	/* Transmit EEE Low Power Timer register */
-	u32	res_c0[8];
-	u32	statn_config;	/* Statistics configuration register */
-	u32	res_e4[7];
-
-	/* memac statistics counter registers */
-	u32	rx_eoct_l;	/* Rx ethernet octests lower */
-	u32	rx_eoct_u;	/* Rx ethernet octests upper */
-	u32	rx_oct_l;	/* Rx octests lower */
-	u32	rx_oct_u;	/* Rx octests upper */
-	u32	rx_align_err_l;	/* Rx alignment error lower */
-	u32	rx_align_err_u;	/* Rx alignment error upper */
-	u32	rx_pause_frame_l; /* Rx valid pause frame upper */
-	u32	rx_pause_frame_u; /* Rx valid pause frame upper */
-	u32	rx_frame_l;	/* Rx frame counter lower */
-	u32	rx_frame_u;	/* Rx frame counter upper */
-	u32	rx_frame_crc_err_l; /* Rx frame check sequence error lower */
-	u32	rx_frame_crc_err_u; /* Rx frame check sequence error upper */
-	u32	rx_vlan_l;	/* Rx VLAN frame lower */
-	u32	rx_vlan_u;	/* Rx VLAN frame upper */
-	u32	rx_err_l;	/* Rx frame error lower */
-	u32	rx_err_u;	/* Rx frame error upper */
-	u32	rx_uni_l;	/* Rx unicast frame lower */
-	u32	rx_uni_u;	/* Rx unicast frame upper */
-	u32	rx_multi_l;	/* Rx multicast frame lower */
-	u32	rx_multi_u;	/* Rx multicast frame upper */
-	u32	rx_brd_l;	/* Rx broadcast frame lower */
-	u32	rx_brd_u;	/* Rx broadcast frame upper */
-	u32	rx_drop_l;	/* Rx dropped packets lower */
-	u32	rx_drop_u;	/* Rx dropped packets upper */
-	u32	rx_pkt_l;	/* Rx packets lower */
-	u32	rx_pkt_u;	/* Rx packets upper */
-	u32	rx_undsz_l;	/* Rx undersized packet lower */
-	u32	rx_undsz_u;	/* Rx undersized packet upper */
-	u32	rx_64_l;	/* Rx 64 oct packet lower */
-	u32	rx_64_u;	/* Rx 64 oct packet upper */
-	u32	rx_127_l;	/* Rx 65 to 127 oct packet lower */
-	u32	rx_127_u;	/* Rx 65 to 127 oct packet upper */
-	u32	rx_255_l;	/* Rx 128 to 255 oct packet lower */
-	u32	rx_255_u;	/* Rx 128 to 255 oct packet upper */
-	u32	rx_511_l;	/* Rx 256 to 511 oct packet lower */
-	u32	rx_511_u;	/* Rx 256 to 511 oct packet upper */
-	u32	rx_1023_l;	/* Rx 512 to 1023 oct packet lower */
-	u32	rx_1023_u;	/* Rx 512 to 1023 oct packet upper */
-	u32	rx_1518_l;	/* Rx 1024 to 1518 oct packet lower */
-	u32	rx_1518_u;	/* Rx 1024 to 1518 oct packet upper */
-	u32	rx_1519_l;	/* Rx 1519 to max oct packet lower */
-	u32	rx_1519_u;	/* Rx 1519 to max oct packet upper */
-	u32	rx_oversz_l;	/* Rx oversized packet lower */
-	u32	rx_oversz_u;	/* Rx oversized packet upper */
-	u32	rx_jabber_l;	/* Rx Jabber packet lower */
-	u32	rx_jabber_u;	/* Rx Jabber packet upper */
-	u32	rx_frag_l;	/* Rx Fragment packet lower */
-	u32	rx_frag_u;	/* Rx Fragment packet upper */
-	u32	rx_cnp_l;	/* Rx control packet lower */
-	u32	rx_cnp_u;	/* Rx control packet upper */
-	u32	rx_drntp_l;	/* Rx dripped not truncated packet lower */
-	u32	rx_drntp_u;	/* Rx dripped not truncated packet upper */
-	u32	res_1d0[0xc];
-
-	u32	tx_eoct_l;	/* Tx ethernet octests lower */
-	u32	tx_eoct_u;	/* Tx ethernet octests upper */
-	u32	tx_oct_l;	/* Tx octests lower */
-	u32	tx_oct_u;	/* Tx octests upper */
-	u32	res_210[0x2];
-	u32	tx_pause_frame_l; /* Tx valid pause frame lower */
-	u32	tx_pause_frame_u; /* Tx valid pause frame upper */
-	u32	tx_frame_l;	/* Tx frame counter lower */
-	u32	tx_frame_u;	/* Tx frame counter upper */
-	u32	tx_frame_crc_err_l; /* Tx frame check sequence error lower */
-	u32	tx_frame_crc_err_u; /* Tx frame check sequence error upper */
-	u32	tx_vlan_l;	/* Tx VLAN frame lower */
-	u32	tx_vlan_u;	/* Tx VLAN frame upper */
-	u32	tx_frame_err_l;	/* Tx frame error lower */
-	u32	tx_frame_err_u;	/* Tx frame error upper */
-	u32	tx_uni_l;	/* Tx unicast frame lower */
-	u32	tx_uni_u;	/* Tx unicast frame upper */
-	u32	tx_multi_l;	/* Tx multicast frame lower */
-	u32	tx_multi_u;	/* Tx multicast frame upper */
-	u32	tx_brd_l;	/* Tx broadcast frame lower */
-	u32	tx_brd_u;	/* Tx broadcast frame upper */
-	u32	res_258[0x2];
-	u32	tx_pkt_l;	/* Tx packets lower */
-	u32	tx_pkt_u;	/* Tx packets upper */
-	u32	tx_undsz_l;	/* Tx undersized packet lower */
-	u32	tx_undsz_u;	/* Tx undersized packet upper */
-	u32	tx_64_l;	/* Tx 64 oct packet lower */
-	u32	tx_64_u;	/* Tx 64 oct packet upper */
-	u32	tx_127_l;	/* Tx 65 to 127 oct packet lower */
-	u32	tx_127_u;	/* Tx 65 to 127 oct packet upper */
-	u32	tx_255_l;	/* Tx 128 to 255 oct packet lower */
-	u32	tx_255_u;	/* Tx 128 to 255 oct packet upper */
-	u32	tx_511_l;	/* Tx 256 to 511 oct packet lower */
-	u32	tx_511_u;	/* Tx 256 to 511 oct packet upper */
-	u32	tx_1023_l;	/* Tx 512 to 1023 oct packet lower */
-	u32	tx_1023_u;	/* Tx 512 to 1023 oct packet upper */
-	u32	tx_1518_l;	/* Tx 1024 to 1518 oct packet lower */
-	u32	tx_1518_u;	/* Tx 1024 to 1518 oct packet upper */
-	u32	tx_1519_l;	/* Tx 1519 to max oct packet lower */
-	u32	tx_1519_u;	/* Tx 1519 to max oct packet upper */
-	u32	res_2a8[0x6];
-	u32	tx_cnp_l;	/* Tx control packet lower */
-	u32	tx_cnp_u;	/* Tx control packet upper */
-	u32	res_2c8[0xe];
-
-	/* Line interface control register */
-	u32 if_mode;		/* interface mode control */
-	u32 if_status;		/* interface status */
-	u32 res_308[0xe];
-
-	/* HiGig/2 Register */
-	u32 hg_config;	/* HiGig2 control and configuration */
-	u32 res_344[0x3];
-	u32 hg_pause_quanta;	/* HiGig2 pause quanta */
-	u32 res_354[0x3];
-	u32 hg_pause_thresh;	/* HiGig2 pause quanta threshold */
-	u32 res_364[0x3];
-	u32 hgrx_pause_status;	/* HiGig2 rx pause quanta status */
-	u32 hg_fifos_status;	/* HiGig2 fifos status */
-	u32 rhm;	/* Rx HiGig2 message counter register */
-	u32 thm;/* Tx HiGig2 message counter register */
-	u32 res_380[0x320];
-};
-
-/* COMMAND_CONFIG - command and configuration register */
-#define MEMAC_CMD_CFG_RX_EN		0x00000002 /* MAC Rx path enable */
-#define MEMAC_CMD_CFG_TX_EN		0x00000001 /* MAC Tx path enable */
-#define MEMAC_CMD_CFG_RXTX_EN	(MEMAC_CMD_CFG_RX_EN | MEMAC_CMD_CFG_TX_EN)
-#define MEMAC_CMD_CFG_NO_LEN_CHK 0x20000 /* Payload length check disable */
-
-/* HASHTABLE_CTRL - Hashtable control register */
-#define HASHTABLE_CTRL_MCAST_EN	0x00000200 /* enable mulitcast Rx hash */
-#define HASHTABLE_CTRL_ADDR_MASK	0x000001ff
-
-/* TX_IPG_LENGTH - Transmit inter-packet gap length register */
-#define TX_IPG_LENGTH_IPG_LEN_MASK	0x000003ff
-
-/* IMASK - interrupt mask register */
-#define IMASK_MDIO_SCAN_EVENT	0x00010000 /* MDIO scan event mask */
-#define IMASK_MDIO_CMD_CMPL	0x00008000 /* MDIO cmd completion mask */
-#define IMASK_REM_FAULT		0x00004000 /* remote fault mask */
-#define IMASK_LOC_FAULT		0x00002000 /* local fault mask */
-#define IMASK_TX_ECC_ER		0x00001000 /* Tx frame ECC error mask */
-#define IMASK_TX_FIFO_UNFL	0x00000800 /* Tx FIFO underflow mask */
-#define IMASK_TX_ER		0x00000200 /* Tx frame error mask */
-#define IMASK_RX_FIFO_OVFL	0x00000100 /* Rx FIFO overflow mask */
-#define IMASK_RX_ECC_ER		0x00000080 /* Rx frame ECC error mask */
-#define IMASK_RX_JAB_FRM	0x00000040 /* Rx jabber frame mask */
-#define IMASK_RX_OVRSZ_FRM	0x00000020 /* Rx oversized frame mask */
-#define IMASK_RX_RUNT_FRM	0x00000010 /* Rx runt frame mask */
-#define IMASK_RX_FRAG_FRM	0x00000008 /* Rx fragment frame mask */
-#define IMASK_RX_LEN_ER		0x00000004 /* Rx payload length error mask */
-#define IMASK_RX_CRC_ER		0x00000002 /* Rx CRC error mask */
-#define IMASK_RX_ALIGN_ER	0x00000001 /* Rx alignment error mask */
-
-#define IMASK_MASK_ALL		0x00000000
-
-/* IEVENT - interrupt event register */
-#define IEVENT_MDIO_SCAN_EVENT	0x00010000 /* MDIO scan event */
-#define IEVENT_MDIO_CMD_CMPL	0x00008000 /* MDIO cmd completion */
-#define IEVENT_REM_FAULT	0x00004000 /* remote fault */
-#define IEVENT_LOC_FAULT	0x00002000 /* local fault */
-#define IEVENT_TX_ECC_ER	0x00001000 /* Tx frame ECC error */
-#define IEVENT_TX_FIFO_UNFL	0x00000800 /* Tx FIFO underflow */
-#define IEVENT_TX_ER		0x00000200 /* Tx frame error */
-#define IEVENT_RX_FIFO_OVFL	0x00000100 /* Rx FIFO overflow */
-#define IEVENT_RX_ECC_ER	0x00000080 /* Rx frame ECC error */
-#define IEVENT_RX_JAB_FRM	0x00000040 /* Rx jabber frame */
-#define IEVENT_RX_OVRSZ_FRM	0x00000020 /* Rx oversized frame */
-#define IEVENT_RX_RUNT_FRM	0x00000010 /* Rx runt frame */
-#define IEVENT_RX_FRAG_FRM	0x00000008 /* Rx fragment frame */
-#define IEVENT_RX_LEN_ER	0x00000004 /* Rx payload length error */
-#define IEVENT_RX_CRC_ER	0x00000002 /* Rx CRC error */
-#define IEVENT_RX_ALIGN_ER	0x00000001 /* Rx alignment error */
-
-#define IEVENT_CLEAR_ALL	0xffffffff
-
-/* IF_MODE - Interface Mode Register */
-#define IF_MODE_EN_AUTO	0x00008000 /* 1 - Enable automatic speed selection */
-#define IF_MODE_SETSP_100M	0x00000000 /* 00 - 100Mbps RGMII */
-#define IF_MODE_SETSP_10M	0x00002000 /* 01 - 10Mbps RGMII */
-#define IF_MODE_SETSP_1000M	0x00004000 /* 10 - 1000Mbps RGMII */
-#define IF_MODE_SETSP_MASK	0x00006000 /* setsp mask bits */
-#define IF_MODE_XGMII	0x00000000 /* 00- XGMII(10) interface mode */
-#define IF_MODE_GMII		0x00000002 /* 10- GMII interface mode */
-#define IF_MODE_MASK	0x00000003 /* mask for mode interface mode */
-#define IF_MODE_RG		0x00000004 /* 1- RGMII */
-#define IF_MODE_RM		0x00000008 /* 1- RGMII */
-
-#define IF_DEFAULT	(IF_GMII)
-
-/* Internal PHY Registers - SGMII */
-#define PHY_SGMII_CR_PHY_RESET      0x8000
-#define PHY_SGMII_CR_RESET_AN       0x0200
-#define PHY_SGMII_CR_DEF_VAL        0x1140
-#define PHY_SGMII_DEV_ABILITY_SGMII 0x4001
-#define PHY_SGMII_IF_MODE_AN        0x0002
-#define PHY_SGMII_IF_MODE_SGMII     0x0001
-
-struct memac_mdio_controller {
-	u32	res0[0xc];
-	u32	mdio_stat;	/* MDIO configuration and status */
-	u32	mdio_ctl;	/* MDIO control */
-	u32	mdio_data;	/* MDIO data */
-	u32	mdio_addr;	/* MDIO address */
-};
-
-#define MDIO_STAT_CLKDIV(x)	(((x>>1) & 0xff) << 8)
-#define MDIO_STAT_BSY		(1 << 0)
-#define MDIO_STAT_RD_ER		(1 << 1)
-#define MDIO_STAT_PRE		(1 << 5)
-#define MDIO_STAT_ENC		(1 << 6)
-#define MDIO_STAT_HOLD_15_CLK	(7 << 2)
-#define MDIO_STAT_NEG		(1 << 23)
-
-#define MDIO_CTL_DEV_ADDR(x)	(x & 0x1f)
-#define MDIO_CTL_PORT_ADDR(x)	((x & 0x1f) << 5)
-#define MDIO_CTL_PRE_DIS	(1 << 10)
-#define MDIO_CTL_SCAN_EN	(1 << 11)
-#define MDIO_CTL_POST_INC	(1 << 14)
-#define MDIO_CTL_READ		(1 << 15)
-
-#define MDIO_DATA(x)		(x & 0xffff)
-#define MDIO_DATA_BSY		(1 << 31)
-
-struct fsl_enet_mac;
-
-void init_memac(struct fsl_enet_mac *mac, void *base, void *phyregs,
-		int max_rx_len);
-
-#endif
diff --git a/arch/powerpc/include/asm/fsl_secure_boot.h b/arch/powerpc/include/asm/fsl_secure_boot.h
index 49f6814..8f794ef 100644
--- a/arch/powerpc/include/asm/fsl_secure_boot.h
+++ b/arch/powerpc/include/asm/fsl_secure_boot.h
@@ -67,5 +67,24 @@
 #define CONFIG_FSL_ISBC_KEY_EXT
 #endif
 
+#ifndef CONFIG_FIT_SIGNATURE
+/* The bootscript header address is different for B4860 because the NOR
+ * mapping is different on B4 due to reduced NOR size.
+ */
+#if defined(CONFIG_B4860QDS)
+#define CONFIG_BOOTSCRIPT_HDR_ADDR	0xecc00000
+#elif defined(CONFIG_FSL_CORENET)
+#define CONFIG_BOOTSCRIPT_HDR_ADDR	0xe8e00000
+#elif defined(CONFIG_BSC9132QDS)
+#define CONFIG_BOOTSCRIPT_HDR_ADDR	0x88020000
+#elif defined(CONFIG_C29XPCIE)
+#define CONFIG_BOOTSCRIPT_HDR_ADDR	0xec020000
+#else
+#define CONFIG_BOOTSCRIPT_HDR_ADDR	0xee020000
+#endif
+
+#include <config_fsl_secboot.h>
+#endif
+
 #endif
 #endif
diff --git a/arch/powerpc/lib/board.c b/arch/powerpc/lib/board.c
index 91645d3..5ea29cc 100644
--- a/arch/powerpc/lib/board.c
+++ b/arch/powerpc/lib/board.c
@@ -890,7 +890,7 @@ void board_init_r(gd_t *id, ulong dest_addr)
 #if defined(CONFIG_CMD_NET)
 	WATCHDOG_RESET();
 	puts("Net:   ");
-	eth_initialize(bd);
+	eth_initialize();
 #endif
 
 #if defined(CONFIG_CMD_NET) && defined(CONFIG_RESET_PHY_R)