summaryrefslogtreecommitdiff
path: root/arch/powerpc/include
diff options
context:
space:
mode:
authorYork Sun <yorksun@freescale.com>2012-10-08 07:44:30 +0000
committerAndy Fleming <afleming@freescale.com>2012-10-22 14:31:32 -0500
commitffd06e0231ac3fd0c5810f39f6e23527948df1c7 (patch)
tree7d648c2c312b9cc7a75c0350101aacc67afca399 /arch/powerpc/include
parent3f0997b3255c1498ac92453aa3a7a1cc95914dfd (diff)
downloadu-boot-imx-ffd06e0231ac3fd0c5810f39f6e23527948df1c7.zip
u-boot-imx-ffd06e0231ac3fd0c5810f39f6e23527948df1c7.tar.gz
u-boot-imx-ffd06e0231ac3fd0c5810f39f6e23527948df1c7.tar.bz2
powerpc/mpc85xx: Rewrite spin table to comply with ePAPR v1.1
Move spin table to cached memory to comply with ePAPR v1.1. Load R3 with 64-bit value if CONFIG_SYS_PPC64 is defined. 'M' bit is set for DDR TLB to maintain cache coherence. See details in doc/README.mpc85xx-spin-table. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
Diffstat (limited to 'arch/powerpc/include')
-rw-r--r--arch/powerpc/include/asm/config_mpc85xx.h3
1 files changed, 3 insertions, 0 deletions
diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h
index 92ca2ad..8a7c81b 100644
--- a/arch/powerpc/include/asm/config_mpc85xx.h
+++ b/arch/powerpc/include/asm/config_mpc85xx.h
@@ -416,6 +416,7 @@
#define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
#elif defined(CONFIG_PPC_P5020) /* also supports P5010 */
+#define CONFIG_SYS_PPC64 /* 64-bit core */
#define CONFIG_SYS_FSL_QORIQ_CHASSIS1
#define CONFIG_MAX_CPUS 2
#define CONFIG_SYS_FSL_NUM_CC_PLLS 2
@@ -485,6 +486,7 @@
#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
#elif defined(CONFIG_PPC_T4240)
+#define CONFIG_SYS_PPC64 /* 64-bit core */
#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
#define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */
#define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */
@@ -516,6 +518,7 @@
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
#elif defined(CONFIG_PPC_B4860)
+#define CONFIG_SYS_PPC64 /* 64-bit core */
#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
#define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */
#define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */