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authorKumar Gala <galak@kernel.crashing.org>2011-02-18 05:40:54 -0600
committerKumar Gala <galak@kernel.crashing.org>2011-04-28 22:09:24 -0500
commit66412c6371cfd6e056679abedea7d6fafe6a0422 (patch)
tree261d51ec7e7c2a22f0bd5db5fca43d4fc9910aeb /arch/powerpc/include
parentd90fdba6ca0b08c77cced6e914609e3696dd5909 (diff)
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powerpc/85xx: Change timebase divisor to be defined per processor
Introduce new CONFIG_SYS_FSL_TBCLK_DIV on 85xx platforms because different SoCs have different divisor amounts. All the PQ3 parts are /8, the P4080/P4080 is /16, and P2040/P3041/P5020 are /32. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'arch/powerpc/include')
-rw-r--r--arch/powerpc/include/asm/config_mpc85xx.h6
1 files changed, 6 insertions, 0 deletions
diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h
index ccf703b..41c2d20 100644
--- a/arch/powerpc/include/asm/config_mpc85xx.h
+++ b/arch/powerpc/include/asm/config_mpc85xx.h
@@ -264,6 +264,7 @@
#define CONFIG_SYS_NUM_FM1_DTSEC 5
#define CONFIG_NUM_DDR_CONTROLLERS 1
#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
+#define CONFIG_SYS_FSL_TBCLK_DIV 32
#define CONFIG_SYS_FSL_USB1_PHY_ENABLE
#define CONFIG_SYS_FSL_USB2_PHY_ENABLE
#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
@@ -278,6 +279,7 @@
#define CONFIG_SYS_NUM_FM1_10GEC 1
#define CONFIG_NUM_DDR_CONTROLLERS 1
#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
+#define CONFIG_SYS_FSL_TBCLK_DIV 32
#define CONFIG_SYS_FSL_USB1_PHY_ENABLE
#define CONFIG_SYS_FSL_USB2_PHY_ENABLE
#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
@@ -288,6 +290,7 @@
#define CONFIG_SYS_FSL_NUM_LAWS 32
#define CONFIG_SYS_FSL_SEC_COMPAT 4
#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
+#define CONFIG_SYS_FSL_TBCLK_DIV 16
#elif defined(CONFIG_PPC_P4080)
#define CONFIG_MAX_CPUS 8
@@ -301,6 +304,7 @@
#define CONFIG_SYS_NUM_FM2_10GEC 1
#define CONFIG_NUM_DDR_CONTROLLERS 2
#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
+#define CONFIG_SYS_FSL_TBCLK_DIV 16
#define CONFIG_SYS_FSL_ERRATUM_CPC_A002
#define CONFIG_SYS_FSL_ERRATUM_CPC_A003
#define CONFIG_SYS_FSL_ERRATUM_DDR_A003
@@ -325,6 +329,7 @@
#define CONFIG_SYS_NUM_FM1_10GEC 1
#define CONFIG_NUM_DDR_CONTROLLERS 1
#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
+#define CONFIG_SYS_FSL_TBCLK_DIV 32
#define CONFIG_SYS_FSL_USB1_PHY_ENABLE
#define CONFIG_SYS_FSL_USB2_PHY_ENABLE
#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
@@ -339,6 +344,7 @@
#define CONFIG_SYS_NUM_FM1_10GEC 1
#define CONFIG_NUM_DDR_CONTROLLERS 2
#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
+#define CONFIG_SYS_FSL_TBCLK_DIV 32
#define CONFIG_SYS_FSL_USB1_PHY_ENABLE
#define CONFIG_SYS_FSL_USB2_PHY_ENABLE
#define CONFIG_SYS_FSL_ERRATUM_ESDHC111