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authorWolfgang Denk <wd@denx.de>2011-11-08 07:44:52 +0100
committerWolfgang Denk <wd@denx.de>2011-11-08 07:44:52 +0100
commit5721385b187b3154c7768e6c182501022f4e2e45 (patch)
tree539198587e4c6f6d03f2065bfebc4bb697773300 /arch/powerpc/include
parent688d8f33f27ea596efb6632388ee60360996eed0 (diff)
parent6be55ee2252c364b16d99537bf9fe7d96d5c77b4 (diff)
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Merge branch 'master' of git://git.denx.de/u-boot-mpc83xx
* 'master' of git://git.denx.de/u-boot-mpc83xx: powerpc/mpc83xx: Add 33.33MHz support for mpc8360emds powerpc/mpc83xx: Add 512MB DDR support for mpc8360emds mpc83xx: Rename CONFIG_SYS_DDR_CONFIG and cleanup DDR csbnds code mpc83xx: Cleanup usage of LBC constants mpc83xx: Cleanup usage of DDR constants mpc83xx: Cleanup usage of BAT constants mpc83xx: cosmetic: vme8349.h checkpatch compliance mpc83xx: cosmetic: ve8313.h checkpatch compliance mpc83xx: cosmetic: sbc8349.h checkpatch compliance mpc83xx: cosmetic: mpc8308_p1m.h checkpatch compliance mpc83xx: cosmetic: kmeter1.h checkpatch compliance mpc83xx: cosmetic: TQM834x.h checkpatch compliance mpc83xx: cosmetic: SIMPC8313.h checkpatch compliance mpc83xx: cosmetic: MVBLM7.h checkpatch compliance mpc83xx: cosmetic: MPC837XERDB.h checkpatch compliance mpc83xx: cosmetic: MPC837XEMDS.h checkpatch compliance mpc83xx: cosmetic: MPC8360ERDK.h checkpatch compliance mpc83xx: cosmetic: MPC8360EMDS.h checkpatch compliance mpc83xx: cosmetic: MPC8349ITX.h checkpatch compliance mpc83xx: cosmetic: MPC8349EMDS.h checkpatch compliance mpc83xx: cosmetic: MPC832XEMDS.h checkpatch compliance mpc83xx: cosmetic: MPC8323ERDB.h checkpatch compliance mpc83xx: cosmetic: MPC8315ERDB.h checkpatch compliance mpc83xx: cosmetic: MPC8313ERDB.h checkpatch compliance mpc83xx: cosmetic: MPC8308RDB.h checkpatch compliance mpc83xx: cosmetic: MERGERBOX.h checkpatch compliance mpc83xx: Fix ipic structure definition powerpc, mpc83xx: add DDR SDRAM Timing Configuration 3 definitions cosmetic, powerpc, mpc83xx: checkpatch cleanup powerpc/83xx: move km 83xx specific i2c code to km83xx_i2c mpc83xx: fix global timer structure definition
Diffstat (limited to 'arch/powerpc/include')
-rw-r--r--arch/powerpc/include/asm/fsl_lbc.h8
-rw-r--r--arch/powerpc/include/asm/immap_83xx.h11
2 files changed, 13 insertions, 6 deletions
diff --git a/arch/powerpc/include/asm/fsl_lbc.h b/arch/powerpc/include/asm/fsl_lbc.h
index 8695a62..bf572b7 100644
--- a/arch/powerpc/include/asm/fsl_lbc.h
+++ b/arch/powerpc/include/asm/fsl_lbc.h
@@ -50,8 +50,10 @@ void lbc_sdram_init(void);
#define BR_MSEL 0x000000E0
#define BR_MSEL_SHIFT 5
#define BR_MS_GPCM 0x00000000 /* GPCM */
+#if !defined(CONFIG_MPC834x) && !defined(CONFIG_MPC8360)
#define BR_MS_FCM 0x00000020 /* FCM */
-#ifdef CONFIG_MPC83xx
+#endif
+#if defined(CONFIG_MPC834x) || defined(CONFIG_MPC8360)
#define BR_MS_SDRAM 0x00000060 /* SDRAM */
#elif defined(CONFIG_MPC85xx)
#define BR_MS_SDRAM 0x00000000 /* SDRAM */
@@ -138,8 +140,10 @@ void lbc_sdram_init(void);
#define OR_GPCM_EHTR_SHIFT 1
#define OR_GPCM_EHTR_CLEAR 0x00000000
#define OR_GPCM_EHTR_SET 0x00000002
+#if !defined(CONFIG_MPC8308)
#define OR_GPCM_EAD 0x00000001
#define OR_GPCM_EAD_SHIFT 0
+#endif
/* helpers to convert values into an OR address mask (GPCM mode) */
#define P2SZ_TO_AM(s) ((~((s) - 1)) & 0xffff8000) /* must be pow of 2 */
@@ -196,8 +200,10 @@ void lbc_sdram_init(void);
#define OR_SDRAM_XAM_SHIFT 13
#define OR_SDRAM_COLS 0x00001C00
#define OR_SDRAM_COLS_SHIFT 10
+#define OR_SDRAM_MIN_COLS 7
#define OR_SDRAM_ROWS 0x000001C0
#define OR_SDRAM_ROWS_SHIFT 6
+#define OR_SDRAM_MIN_ROWS 9
#define OR_SDRAM_PMSEL 0x00000020
#define OR_SDRAM_PMSEL_SHIFT 5
#define OR_SDRAM_EAD 0x00000001
diff --git a/arch/powerpc/include/asm/immap_83xx.h b/arch/powerpc/include/asm/immap_83xx.h
index 8d4c9cb..2ba502a 100644
--- a/arch/powerpc/include/asm/immap_83xx.h
+++ b/arch/powerpc/include/asm/immap_83xx.h
@@ -113,7 +113,7 @@ typedef struct gtm83xx {
u8 cfr1; /* Timer1/2 Configuration */
u8 res0[3];
u8 cfr2; /* Timer3/4 Configuration */
- u8 res1[10];
+ u8 res1[11];
u16 mdr1; /* Timer1 Mode Register */
u16 mdr2; /* Timer2 Mode Register */
u16 rfr1; /* Timer1 Reference Register */
@@ -150,11 +150,12 @@ typedef struct ipic83xx {
u32 sipnr_h; /* System Internal Interrupt Pending Register - High */
u32 sipnr_l; /* System Internal Interrupt Pending Register - Low */
u32 siprr_a; /* System Internal Interrupt Group A Priority Register */
- u8 res0[8];
+ u32 siprr_b; /* System Internal Interrupt Group B Priority Register */
+ u32 siprr_c; /* System Internal Interrupt Group C Priority Register */
u32 siprr_d; /* System Internal Interrupt Group D Priority Register */
u32 simsr_h; /* System Internal Interrupt Mask Register - High */
u32 simsr_l; /* System Internal Interrupt Mask Register - Low */
- u8 res1[4];
+ u32 sicnr; /* System Internal Interrupt Control Register */
u32 sepnr; /* System External Interrupt Pending Register */
u32 smprr_a; /* System Mixed Interrupt Group A Priority Register */
u32 smprr_b; /* System Mixed Interrupt Group B Priority Register */
@@ -163,14 +164,14 @@ typedef struct ipic83xx {
u32 sersr; /* System Error Status Register */
u32 sermr; /* System Error Mask Register */
u32 sercr; /* System Error Control Register */
- u8 res2[4];
+ u32 sepcr; /* System External Interrupt Polarity Control Register */
u32 sifcr_h; /* System Internal Interrupt Force Register - High */
u32 sifcr_l; /* System Internal Interrupt Force Register - Low */
u32 sefcr; /* System External Interrupt Force Register */
u32 serfr; /* System Error Force Register */
u32 scvcr; /* System Critical Interrupt Vector Register */
u32 smvcr; /* System Management Interrupt Vector Register */
- u8 res3[0x98];
+ u8 res[0x98];
} ipic83xx_t;
/*