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authorTom Rini <trini@ti.com>2012-09-25 12:23:55 -0700
committerTom Rini <trini@ti.com>2012-09-25 12:23:55 -0700
commit5675b509165b67465a20e5cf71e07f40b449ef0c (patch)
tree9886f3e8fa8734ec9f8d9cb484fcaa87ff70203f /arch/powerpc/include
parentee1f4caaa2a3f79d692155eec8a4c7289d60e106 (diff)
parentd69dba367aed051663d0ee1ece013c8232bfa9f5 (diff)
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Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx
Diffstat (limited to 'arch/powerpc/include')
-rw-r--r--arch/powerpc/include/asm/config.h4
-rw-r--r--arch/powerpc/include/asm/config_mpc85xx.h133
-rw-r--r--arch/powerpc/include/asm/fsl_ddr_dimm_params.h1
-rw-r--r--arch/powerpc/include/asm/fsl_ddr_sdram.h8
-rw-r--r--arch/powerpc/include/asm/fsl_ifc.h18
-rw-r--r--arch/powerpc/include/asm/fsl_law.h13
-rw-r--r--arch/powerpc/include/asm/fsl_serdes.h1
-rw-r--r--arch/powerpc/include/asm/fsl_srio.h8
-rw-r--r--arch/powerpc/include/asm/immap_85xx.h101
-rw-r--r--arch/powerpc/include/asm/io.h20
-rw-r--r--arch/powerpc/include/asm/mmu.h4
-rw-r--r--arch/powerpc/include/asm/mp.h6
-rw-r--r--arch/powerpc/include/asm/processor.h8
13 files changed, 184 insertions, 141 deletions
diff --git a/arch/powerpc/include/asm/config.h b/arch/powerpc/include/asm/config.h
index d138636..67cea01 100644
--- a/arch/powerpc/include/asm/config.h
+++ b/arch/powerpc/include/asm/config.h
@@ -29,6 +29,10 @@
#include <asm/config_mpc86xx.h>
#endif
+#ifndef HWCONFIG_BUFFER_SIZE
+ #define HWCONFIG_BUFFER_SIZE 256
+#endif
+
/* CONFIG_HARD_SPI triggers SPI bus initialization in PowerPC */
#if defined(CONFIG_MPC8XXX_SPI) || defined(CONFIG_FSL_ESPI)
# ifndef CONFIG_HARD_SPI
diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h
index b6c44bb..aa27741 100644
--- a/arch/powerpc/include/asm/config_mpc85xx.h
+++ b/arch/powerpc/include/asm/config_mpc85xx.h
@@ -37,6 +37,7 @@
#if defined(CONFIG_MPC8536)
#define CONFIG_MAX_CPUS 1
#define CONFIG_SYS_FSL_NUM_LAWS 12
+#define CONFIG_SYS_PPC_E500_DEBUG_TLB 1
#define CONFIG_SYS_FSL_SEC_COMPAT 2
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
@@ -54,12 +55,14 @@
#elif defined(CONFIG_MPC8544)
#define CONFIG_MAX_CPUS 1
#define CONFIG_SYS_FSL_NUM_LAWS 10
+#define CONFIG_SYS_PPC_E500_DEBUG_TLB 0
#define CONFIG_SYS_FSL_SEC_COMPAT 2
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
#elif defined(CONFIG_MPC8548)
#define CONFIG_MAX_CPUS 1
#define CONFIG_SYS_FSL_NUM_LAWS 10
+#define CONFIG_SYS_PPC_E500_DEBUG_TLB 0
#define CONFIG_SYS_FSL_SEC_COMPAT 2
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
#define CONFIG_SYS_FSL_ERRATUM_NMG_DDR120
@@ -113,6 +116,7 @@
#elif defined(CONFIG_MPC8572)
#define CONFIG_MAX_CPUS 2
#define CONFIG_SYS_FSL_NUM_LAWS 12
+#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
#define CONFIG_SYS_FSL_SEC_COMPAT 2
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
#define CONFIG_SYS_FSL_ERRATUM_DDR_115
@@ -191,33 +195,6 @@
#define CONFIG_SYS_FSL_ERRATUM_P1010_A003549
#define CONFIG_SYS_FSL_ERRATUM_IFC_A003399
-/* P1015 is single core version of P1024 */
-#elif defined(CONFIG_P1015)
-#define CONFIG_MAX_CPUS 1
-#define CONFIG_SYS_FSL_NUM_LAWS 12
-#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
-#define CONFIG_TSECV2
-#define CONFIG_FSL_PCIE_DISABLE_ASPM
-#define CONFIG_SYS_FSL_SEC_COMPAT 2
-#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
-#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
-#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
-
-/* P1016 is single core version of P1025 */
-#elif defined(CONFIG_P1016)
-#define CONFIG_MAX_CPUS 1
-#define CONFIG_SYS_FSL_NUM_LAWS 12
-#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
-#define CONFIG_TSECV2
-#define CONFIG_FSL_PCIE_DISABLE_ASPM
-#define CONFIG_SYS_FSL_SEC_COMPAT 2
-#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
-#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
-#define QE_MURAM_SIZE 0x6000UL
-#define MAX_QE_RISC 1
-#define QE_NUM_OF_SNUM 28
-#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
-
/* P1017 is single core version of P1023 */
#elif defined(CONFIG_P1017)
#define CONFIG_MAX_CPUS 1
@@ -333,30 +310,7 @@
#define CONFIG_SYS_FSL_RMU
#define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
-#elif defined(CONFIG_PPC_P2040)
-#define CONFIG_MAX_CPUS 4
-#define CONFIG_SYS_FSL_NUM_CC_PLLS 2
-#define CONFIG_SYS_FSL_NUM_LAWS 32
-#define CONFIG_SYS_FSL_SEC_COMPAT 4
-#define CONFIG_SYS_NUM_FMAN 1
-#define CONFIG_SYS_NUM_FM1_DTSEC 5
-#define CONFIG_NUM_DDR_CONTROLLERS 1
-#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
-#define CONFIG_SYS_FSL_TBCLK_DIV 32
-#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
-#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
-#define CONFIG_SYS_FSL_USB1_PHY_ENABLE
-#define CONFIG_SYS_FSL_USB2_PHY_ENABLE
-#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
-#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
-#define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011
-#define CONFIG_SYS_FSL_ERRATUM_CPU_A003999
-#define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
-#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
-#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
-#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
-
-#elif defined(CONFIG_PPC_P2041)
+#elif defined(CONFIG_PPC_P2041) /* also supports P2040 */
#define CONFIG_MAX_CPUS 4
#define CONFIG_SYS_FSL_NUM_CC_PLLS 2
#define CONFIG_SYS_FSL_NUM_LAWS 32
@@ -380,6 +334,10 @@
#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
+#define CONFIG_SYS_FSL_ERRATUM_A004510
+#define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10
+#define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2 0x11
+#define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
#elif defined(CONFIG_PPC_P3041)
#define CONFIG_MAX_CPUS 4
@@ -399,47 +357,18 @@
#define CONFIG_SYS_FSL_USB2_PHY_ENABLE
#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
+#define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011
#define CONFIG_SYS_FSL_ERRATUM_CPU_A003999
#define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
+#define CONFIG_SYS_FSL_ERRATUM_A004510
+#define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10
+#define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2 0x11
+#define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
-#elif defined(CONFIG_PPC_P3060)
-#define CONFIG_MAX_CPUS 8
-#define CONFIG_SYS_FSL_NUM_CC_PLLS 4
-#define CONFIG_SYS_FSL_NUM_LAWS 32
-#define CONFIG_SYS_FSL_SEC_COMPAT 4
-#define CONFIG_SYS_NUM_FMAN 2
-#define CONFIG_SYS_NUM_FM1_DTSEC 4
-#define CONFIG_SYS_NUM_FM2_DTSEC 4
-#define CONFIG_NUM_DDR_CONTROLLERS 1
-#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
-#define CONFIG_SYS_FSL_TBCLK_DIV 16
-#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
-#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
-#define CONFIG_SYS_FSL_ERRATUM_DDR_A003
-#define CONFIG_SYS_FSL_ERRATUM_CPU_A003999
-#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
-#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
-#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
-
-#elif defined(CONFIG_PPC_P4040)
-#define CONFIG_MAX_CPUS 4
-#define CONFIG_SYS_FSL_NUM_CC_PLLS 4
-#define CONFIG_SYS_FSL_NUM_LAWS 32
-#define CONFIG_SYS_FSL_SEC_COMPAT 4
-#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
-#define CONFIG_SYS_FSL_TBCLK_DIV 16
-#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,p4080-pcie"
-#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
-#define CONFIG_SYS_FSL_ERRATUM_CPU_A003999
-#define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
-#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
-#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
-#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
-
-#elif defined(CONFIG_PPC_P4080)
+#elif defined(CONFIG_PPC_P4080) /* also supports P4040 */
#define CONFIG_MAX_CPUS 8
#define CONFIG_SYS_FSL_NUM_CC_PLLS 4
#define CONFIG_SYS_FSL_NUM_LAWS 32
@@ -474,32 +403,11 @@
#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
#define CONFIG_SYS_FSL_RMU
#define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
+#define CONFIG_SYS_FSL_ERRATUM_A004510
+#define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x20
+#define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xff000000
-/* P5010 is single core version of P5020 */
-#elif defined(CONFIG_PPC_P5010)
-#define CONFIG_MAX_CPUS 1
-#define CONFIG_SYS_FSL_NUM_CC_PLLS 2
-#define CONFIG_SYS_FSL_NUM_LAWS 32
-#define CONFIG_SYS_FSL_SEC_COMPAT 4
-#define CONFIG_FSL_SATA_V2
-#define CONFIG_SYS_NUM_FMAN 1
-#define CONFIG_SYS_NUM_FM1_DTSEC 5
-#define CONFIG_SYS_NUM_FM1_10GEC 1
-#define CONFIG_NUM_DDR_CONTROLLERS 1
-#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
-#define CONFIG_SYS_FSL_TBCLK_DIV 32
-#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
-#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
-#define CONFIG_SYS_FSL_USB1_PHY_ENABLE
-#define CONFIG_SYS_FSL_USB2_PHY_ENABLE
-#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
-#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
-#define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
-#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
-#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
-#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
-
-#elif defined(CONFIG_PPC_P5020)
+#elif defined(CONFIG_PPC_P5020) /* also supports P5010 */
#define CONFIG_MAX_CPUS 2
#define CONFIG_SYS_FSL_NUM_CC_PLLS 2
#define CONFIG_SYS_FSL_NUM_LAWS 32
@@ -521,6 +429,9 @@
#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
+#define CONFIG_SYS_FSL_ERRATUM_A004510
+#define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10
+#define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xc0000000
#elif defined(CONFIG_BSC9131)
#define CONFIG_MAX_CPUS 1
diff --git a/arch/powerpc/include/asm/fsl_ddr_dimm_params.h b/arch/powerpc/include/asm/fsl_ddr_dimm_params.h
index 982b809..ffe4db8 100644
--- a/arch/powerpc/include/asm/fsl_ddr_dimm_params.h
+++ b/arch/powerpc/include/asm/fsl_ddr_dimm_params.h
@@ -43,6 +43,7 @@ typedef struct dimm_params_s {
/* DIMM timing parameters */
unsigned int mtb_ps; /* medium timebase ps, only for ddr3 */
+ unsigned int ftb_10th_ps; /* fine timebase, in 1/10 ps, only for ddr3 */
unsigned int tAA_ps; /* minimum CAS latency time, only for ddr3 */
unsigned int tFAW_ps; /* four active window delay, only for ddr3 */
diff --git a/arch/powerpc/include/asm/fsl_ddr_sdram.h b/arch/powerpc/include/asm/fsl_ddr_sdram.h
index 93639ba..e271342 100644
--- a/arch/powerpc/include/asm/fsl_ddr_sdram.h
+++ b/arch/powerpc/include/asm/fsl_ddr_sdram.h
@@ -76,6 +76,13 @@ typedef ddr3_spd_eeprom_t generic_spd_eeprom_t;
#define FSL_DDR_PAGE_INTERLEAVING 0x1
#define FSL_DDR_BANK_INTERLEAVING 0x2
#define FSL_DDR_SUPERBANK_INTERLEAVING 0x3
+#define FSL_DDR_3WAY_1KB_INTERLEAVING 0xA
+#define FSL_DDR_3WAY_4KB_INTERLEAVING 0xC
+#define FSL_DDR_3WAY_8KB_INTERLEAVING 0xD
+/* placeholder for 4-way interleaving */
+#define FSL_DDR_4WAY_1KB_INTERLEAVING 0x1A
+#define FSL_DDR_4WAY_4KB_INTERLEAVING 0x1C
+#define FSL_DDR_4WAY_8KB_INTERLEAVING 0x1D
/* DDR_SDRAM_CFG - DDR SDRAM Control Configuration
*/
@@ -88,6 +95,7 @@ typedef ddr3_spd_eeprom_t generic_spd_eeprom_t;
#define SDRAM_CFG_SDRAM_TYPE_MASK 0x07000000
#define SDRAM_CFG_SDRAM_TYPE_SHIFT 24
#define SDRAM_CFG_DYN_PWR 0x00200000
+#define SDRAM_CFG_DBW_MASK 0x00180000
#define SDRAM_CFG_32_BE 0x00080000
#define SDRAM_CFG_16_BE 0x00100000
#define SDRAM_CFG_8_BE 0x00040000
diff --git a/arch/powerpc/include/asm/fsl_ifc.h b/arch/powerpc/include/asm/fsl_ifc.h
index 7d95eb4..ba41b73 100644
--- a/arch/powerpc/include/asm/fsl_ifc.h
+++ b/arch/powerpc/include/asm/fsl_ifc.h
@@ -783,12 +783,16 @@ extern void init_early_memctl_regs(void);
#define IFC_BASE_ADDR ((struct fsl_ifc *)CONFIG_SYS_IFC_ADDR)
+#define get_ifc_cspr_ext(i) (in_be32(&(IFC_BASE_ADDR)->cspr_cs[i].cspr_ext))
#define get_ifc_cspr(i) (in_be32(&(IFC_BASE_ADDR)->cspr_cs[i].cspr))
+#define get_ifc_csor_ext(i) (in_be32(&(IFC_BASE_ADDR)->csor_cs[i].csor_ext))
#define get_ifc_csor(i) (in_be32(&(IFC_BASE_ADDR)->csor_cs[i].csor))
#define get_ifc_amask(i) (in_be32(&(IFC_BASE_ADDR)->amask_cs[i].amask))
#define get_ifc_ftim(i, j) (in_be32(&(IFC_BASE_ADDR)->ftim_cs[i].ftim[j]))
+#define set_ifc_cspr_ext(i, v) (out_be32(&(IFC_BASE_ADDR)->cspr_cs[i].cspr_ext, v))
#define set_ifc_cspr(i, v) (out_be32(&(IFC_BASE_ADDR)->cspr_cs[i].cspr, v))
+#define set_ifc_csor_ext(i, v) (out_be32(&(IFC_BASE_ADDR)->csor_cs[i].csor_ext, v))
#define set_ifc_csor(i, v) (out_be32(&(IFC_BASE_ADDR)->csor_cs[i].csor, v))
#define set_ifc_amask(i, v) (out_be32(&(IFC_BASE_ADDR)->amask_cs[i].amask, v))
#define set_ifc_ftim(i, j, v) \
@@ -909,22 +913,24 @@ struct fsl_ifc_gpcm {
*/
struct fsl_ifc {
u32 ifc_rev;
- u32 res1[0x3];
+ u32 res1[0x2];
struct {
+ u32 cspr_ext;
u32 cspr;
- u32 res2[0x2];
+ u32 res2;
} cspr_cs[FSL_IFC_BANK_COUNT];
- u32 res3[0x18];
+ u32 res3[0x19];
struct {
u32 amask;
u32 res4[0x2];
} amask_cs[FSL_IFC_BANK_COUNT];
- u32 res5[0x18];
+ u32 res5[0x17];
struct {
+ u32 csor_ext;
u32 csor;
- u32 res6[0x2];
+ u32 res6;
} csor_cs[FSL_IFC_BANK_COUNT];
- u32 res7[0x18];
+ u32 res7[0x19];
struct {
u32 ftim[4];
u32 res8[0x8];
diff --git a/arch/powerpc/include/asm/fsl_law.h b/arch/powerpc/include/asm/fsl_law.h
index 13caffd..f9cec8e 100644
--- a/arch/powerpc/include/asm/fsl_law.h
+++ b/arch/powerpc/include/asm/fsl_law.h
@@ -60,14 +60,19 @@ enum law_trgt_if {
LAW_TRGT_IF_DDR_1 = 0x10,
LAW_TRGT_IF_DDR_2 = 0x11, /* 2nd controller */
+ LAW_TRGT_IF_DDR_3 = 0x12,
+ LAW_TRGT_IF_DDR_4 = 0x13,
LAW_TRGT_IF_DDR_INTRLV = 0x14,
-
+ LAW_TRGT_IF_DDR_INTLV_34 = 0x15,
+ LAW_TRGT_IF_DDR_INTLV_123 = 0x17,
+ LAW_TRGT_IF_DDR_INTLV_1234 = 0x16,
LAW_TRGT_IF_BMAN = 0x18,
LAW_TRGT_IF_DCSR = 0x1d,
LAW_TRGT_IF_LBC = 0x1f,
LAW_TRGT_IF_QMAN = 0x3c,
};
#define LAW_TRGT_IF_DDR LAW_TRGT_IF_DDR_1
+#define LAW_TRGT_IF_IFC LAW_TRGT_IF_LBC
#else
enum law_trgt_if {
LAW_TRGT_IF_PCI = 0x00,
@@ -86,6 +91,12 @@ enum law_trgt_if {
LAW_TRGT_IF_DPAA_SWP_SRAM = 0x0e,
LAW_TRGT_IF_DDR = 0x0f,
LAW_TRGT_IF_DDR_2 = 0x16, /* 2nd controller */
+ /* place holder for 3-way and 4-way interleaving */
+ LAW_TRGT_IF_DDR_3,
+ LAW_TRGT_IF_DDR_4,
+ LAW_TRGT_IF_DDR_INTLV_34,
+ LAW_TRGT_IF_DDR_INTLV_123,
+ LAW_TRGT_IF_DDR_INTLV_1234,
};
#define LAW_TRGT_IF_DDR_1 LAW_TRGT_IF_DDR
#define LAW_TRGT_IF_PCI_1 LAW_TRGT_IF_PCI
diff --git a/arch/powerpc/include/asm/fsl_serdes.h b/arch/powerpc/include/asm/fsl_serdes.h
index 0f31af1..22525f1 100644
--- a/arch/powerpc/include/asm/fsl_serdes.h
+++ b/arch/powerpc/include/asm/fsl_serdes.h
@@ -41,6 +41,7 @@ enum srds_prtcl {
SGMII_FM2_DTSEC2,
SGMII_FM2_DTSEC3,
SGMII_FM2_DTSEC4,
+ SGMII_FM2_DTSEC5,
SGMII_TSEC1,
SGMII_TSEC2,
SGMII_TSEC3,
diff --git a/arch/powerpc/include/asm/fsl_srio.h b/arch/powerpc/include/asm/fsl_srio.h
index a905a26..dfd8e08 100644
--- a/arch/powerpc/include/asm/fsl_srio.h
+++ b/arch/powerpc/include/asm/fsl_srio.h
@@ -55,10 +55,8 @@ enum atmu_size {
#define atmu_size_bytes(x) (1ULL << ((x & 0x3f) + 1))
extern void srio_init(void);
-#ifdef CONFIG_SRIOBOOT_MASTER
-extern void srio_boot_master(void);
-#ifdef CONFIG_SRIOBOOT_SLAVE_HOLDOFF
-extern void srio_boot_master_release_slave(void);
-#endif
+#ifdef CONFIG_FSL_CORENET
+extern void srio_boot_master(int port);
+extern void srio_boot_master_release_slave(int port);
#endif
#endif
diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h
index 53d563e..7de33a7 100644
--- a/arch/powerpc/include/asm/immap_85xx.h
+++ b/arch/powerpc/include/asm/immap_85xx.h
@@ -1729,6 +1729,7 @@ typedef struct ccsr_gur {
#define FSL_CORENET_DEVDISR2_DTSEC2_2 0x00004000
#define FSL_CORENET_DEVDISR2_DTSEC2_3 0x00002000
#define FSL_CORENET_DEVDISR2_DTSEC2_4 0x00001000
+#define FSL_CORENET_DEVDISR2_DTSEC2_5 0x00000800
#define FSL_CORENET_NUM_DEVDISR 2
u8 res7[8];
u32 powmgtcsr; /* Power management status & control */
@@ -1758,13 +1759,14 @@ typedef struct ccsr_gur {
#define FSL_CORENET_RCWSR5_DDR_SYNC 0x00000080
#define FSL_CORENET_RCWSR5_DDR_SYNC_SHIFT 7
#define FSL_CORENET_RCWSR5_SRDS_EN 0x00002000
+#define FSL_CORENET_RCWSR6_BOOT_LOC 0x0f800000
#define FSL_CORENET_RCWSRn_SRDS_LPD_B2 0x3c000000 /* bits 162..165 */
#define FSL_CORENET_RCWSRn_SRDS_LPD_B3 0x003c0000 /* bits 170..173 */
#define FSL_CORENET_RCWSR7_MCK_TO_PLAT_RAT 0x00400000
#define FSL_CORENET_RCWSR8_HOST_AGT_B1 0x00e00000
#define FSL_CORENET_RCWSR8_HOST_AGT_B2 0x00100000
#define FSL_CORENET_RCWSR11_EC1 0x00c00000 /* bits 360..361 */
-#if defined(CONFIG_PPC_P4080) || defined(CONFIG_PPC_P3060)
+#ifdef CONFIG_PPC_P4080
#define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC1 0x00000000
#define FSL_CORENET_RCWSR11_EC1_FM1_USB1 0x00800000
#define FSL_CORENET_RCWSR11_EC2 0x001c0000 /* bits 363..365 */
@@ -1772,7 +1774,7 @@ typedef struct ccsr_gur {
#define FSL_CORENET_RCWSR11_EC2_FM1_DTSEC2 0x00080000
#define FSL_CORENET_RCWSR11_EC2_USB2 0x00100000
#endif
-#if defined(CONFIG_PPC_P2040) || defined(CONFIG_PPC_P2041) \
+#if defined(CONFIG_PPC_P2041) \
|| defined(CONFIG_PPC_P3041) || defined(CONFIG_PPC_P5020)
#define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC4_RGMII 0x00000000
#define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC4_MII 0x00800000
@@ -1836,7 +1838,13 @@ typedef struct ccsr_gur {
u8 res31[184];
u32 sriopstecr; /* SRIO prescaler timer enable control */
u32 dcsrcr; /* DCSR Control register */
- u8 res32[1784];
+ u8 res31a[56];
+ u32 tp_ityp[64]; /* Topology Initiator Type Register */
+ struct {
+ u32 upper;
+ u32 lower;
+ } tp_cluster[16]; /* Core Cluster n Topology Register */
+ u8 res32[1344];
u32 pmuxcr; /* Pin multiplexing control */
u8 res33[60];
u32 iovselsr; /* I/O voltage selection status */
@@ -1849,6 +1857,18 @@ typedef struct ccsr_gur {
u8 res37[380];
} ccsr_gur_t;
+#define TP_ITYP_AV 0x00000001 /* Initiator available */
+#define TP_ITYP_TYPE(x) (((x) & 0x6) >> 1) /* Initiator Type */
+#define TP_ITYP_TYPE_OTHER 0x0
+#define TP_ITYP_TYPE_PPC 0x1 /* PowerPC */
+#define TP_ITYP_TYPE_SC 0x2 /* StarCore DSP */
+#define TP_ITYP_TYPE_HA 0x3 /* HW Accelerator */
+#define TP_ITYP_THDS(x) (((x) & 0x18) >> 3) /* # threads */
+#define TP_ITYP_VER(x) (((x) & 0xe0) >> 5) /* Initiator Version */
+
+#define TP_CLUSTER_EOC 0x80000000 /* end of clusters */
+#define TP_CLUSTER_INIT_MASK 0x0000003f /* initiator mask */
+
#define FSL_CORENET_DCSR_SZ_MASK 0x00000003
#define FSL_CORENET_DCSR_SZ_4M 0x0
#define FSL_CORENET_DCSR_SZ_1G 0x3
@@ -1890,6 +1910,73 @@ typedef struct ccsr_clk {
u8 res15[0x3dc];
} ccsr_clk_t;
+#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
+typedef struct ccsr_rcpm {
+ u8 res_00[12];
+ u32 tph10sr0; /* Thread PH10 Status Register */
+ u8 res_10[12];
+ u32 tph10setr0; /* Thread PH10 Set Control Register */
+ u8 res_20[12];
+ u32 tph10clrr0; /* Thread PH10 Clear Control Register */
+ u8 res_30[12];
+ u32 tph10psr0; /* Thread PH10 Previous Status Register */
+ u8 res_40[12];
+ u32 twaitsr0; /* Thread Wait Status Register */
+ u8 res_50[96];
+ u32 pcph15sr; /* Physical Core PH15 Status Register */
+ u32 pcph15setr; /* Physical Core PH15 Set Control Register */
+ u32 pcph15clrr; /* Physical Core PH15 Clear Control Register */
+ u32 pcph15psr; /* Physical Core PH15 Prev Status Register */
+ u8 res_c0[16];
+ u32 pcph20sr; /* Physical Core PH20 Status Register */
+ u32 pcph20setr; /* Physical Core PH20 Set Control Register */
+ u32 pcph20clrr; /* Physical Core PH20 Clear Control Register */
+ u32 pcph20psr; /* Physical Core PH20 Prev Status Register */
+ u32 pcpw20sr; /* Physical Core PW20 Status Register */
+ u8 res_e0[12];
+ u32 pcph30sr; /* Physical Core PH30 Status Register */
+ u32 pcph30setr; /* Physical Core PH30 Set Control Register */
+ u32 pcph30clrr; /* Physical Core PH30 Clear Control Register */
+ u32 pcph30psr; /* Physical Core PH30 Prev Status Register */
+ u8 res_100[32];
+ u32 ippwrgatecr; /* IP Power Gating Control Register */
+ u8 res_124[12];
+ u32 powmgtcsr; /* Power Management Control & Status Reg */
+ u8 res_134[12];
+ u32 ippdexpcr[4]; /* IP Powerdown Exception Control Reg */
+ u8 res_150[12];
+ u32 tpmimr0; /* Thread PM Interrupt Mask Reg */
+ u8 res_160[12];
+ u32 tpmcimr0; /* Thread PM Crit Interrupt Mask Reg */
+ u8 res_170[12];
+ u32 tpmmcmr0; /* Thread PM Machine Check Interrupt Mask Reg */
+ u8 res_180[12];
+ u32 tpmnmimr0; /* Thread PM NMI Mask Reg */
+ u8 res_190[12];
+ u32 tmcpmaskcr0; /* Thread Machine Check Mask Control Reg */
+ u32 pctbenr; /* Physical Core Time Base Enable Reg */
+ u32 pctbclkselr; /* Physical Core Time Base Clock Select */
+ u32 tbclkdivr; /* Time Base Clock Divider Register */
+ u8 res_1ac[4];
+ u32 ttbhltcr[4]; /* Thread Time Base Halt Control Register */
+ u32 clpcl10sr; /* Cluster PCL10 Status Register */
+ u32 clpcl10setr; /* Cluster PCL30 Set Control Register */
+ u32 clpcl10clrr; /* Cluster PCL30 Clear Control Register */
+ u32 clpcl10psr; /* Cluster PCL30 Prev Status Register */
+ u32 cddslpsetr; /* Core Domain Deep Sleep Set Register */
+ u32 cddslpclrr; /* Core Domain Deep Sleep Clear Register */
+ u32 cdpwroksetr; /* Core Domain Power OK Set Register */
+ u32 cdpwrokclrr; /* Core Domain Power OK Clear Register */
+ u32 cdpwrensr; /* Core Domain Power Enable Status Register */
+ u32 cddslsr; /* Core Domain Deep Sleep Status Register */
+ u8 res_1e8[8];
+ u32 dslpcntcr[8]; /* Deep Sleep Counter Cfg Register */
+ u8 res_300[3568];
+} ccsr_rcpm_t;
+
+#define ctbenrl pctbenr
+
+#else
typedef struct ccsr_rcpm {
u8 res1[4];
u32 cdozsrl; /* Core Doze Status */
@@ -1926,6 +2013,7 @@ typedef struct ccsr_rcpm {
u32 ctbhltcrl; /* Core Time Base Halt Control */
u8 res18[0xf68];
} ccsr_rcpm_t;
+#endif /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */
#else
typedef struct ccsr_gur {
@@ -2259,8 +2347,7 @@ typedef struct ccsr_gur {
u8 res11a[76];
par_io_t qe_par_io[7];
u8 res11b[1600];
-#elif defined(CONFIG_P1012) || defined(CONFIG_P1016) || \
- defined(CONFIG_P1021) || defined(CONFIG_P1025)
+#elif defined(CONFIG_P1012) || defined(CONFIG_P1021) || defined(CONFIG_P1025)
u8 res11a[12];
u32 iovselsr;
u8 res11b[60];
@@ -2534,6 +2621,7 @@ struct ccsr_rman {
#define CONFIG_SYS_FSL_CORENET_CCM_OFFSET 0x0000
#define CONFIG_SYS_MPC85xx_DDR_OFFSET 0x8000
#define CONFIG_SYS_MPC85xx_DDR2_OFFSET 0x9000
+#define CONFIG_SYS_MPC85xx_DDR3_OFFSET 0xA000
#define CONFIG_SYS_FSL_CORENET_CLK_OFFSET 0xE1000
#define CONFIG_SYS_FSL_CORENET_RCPM_OFFSET 0xE2000
#define CONFIG_SYS_FSL_CORENET_SERDES_OFFSET 0xEA000
@@ -2544,6 +2632,7 @@ struct ccsr_rman {
#define CONFIG_SYS_MPC85xx_ESPI_OFFSET 0x110000
#define CONFIG_SYS_MPC85xx_ESDHC_OFFSET 0x114000
#define CONFIG_SYS_MPC85xx_LBC_OFFSET 0x124000
+#define CONFIG_SYS_MPC85xx_IFC_OFFSET 0x124000
#define CONFIG_SYS_MPC85xx_GPIO_OFFSET 0x130000
#define CONFIG_SYS_FSL_CORENET_RMAN_OFFSET 0x1e0000
#define CONFIG_SYS_MPC85xx_PCIE1_OFFSET 0x200000
@@ -2652,6 +2741,8 @@ struct ccsr_rman {
(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_DDR_OFFSET)
#define CONFIG_SYS_MPC85xx_DDR2_ADDR \
(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_DDR2_OFFSET)
+#define CONFIG_SYS_MPC85xx_DDR3_ADDR \
+ (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_DDR3_OFFSET)
#define CONFIG_SYS_LBC_ADDR \
(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_LBC_OFFSET)
#define CONFIG_SYS_IFC_ADDR \
diff --git a/arch/powerpc/include/asm/io.h b/arch/powerpc/include/asm/io.h
index ec0bfae..9e20861 100644
--- a/arch/powerpc/include/asm/io.h
+++ b/arch/powerpc/include/asm/io.h
@@ -162,7 +162,7 @@ static inline void __raw_writel(unsigned int v, volatile void __iomem *addr)
* is actually performed (i.e. the data has come back) before we start
* executing any following instructions.
*/
-static inline u8 in_8(const volatile unsigned char __iomem *addr)
+extern inline u8 in_8(const volatile unsigned char __iomem *addr)
{
u8 ret;
@@ -173,7 +173,7 @@ static inline u8 in_8(const volatile unsigned char __iomem *addr)
return ret;
}
-static inline void out_8(volatile unsigned char __iomem *addr, u8 val)
+extern inline void out_8(volatile unsigned char __iomem *addr, u8 val)
{
__asm__ __volatile__("sync;\n"
"stb%U0%X0 %1,%0;\n"
@@ -181,7 +181,7 @@ static inline void out_8(volatile unsigned char __iomem *addr, u8 val)
: "r" (val));
}
-static inline u16 in_le16(const volatile unsigned short __iomem *addr)
+extern inline u16 in_le16(const volatile unsigned short __iomem *addr)
{
u16 ret;
@@ -192,7 +192,7 @@ static inline u16 in_le16(const volatile unsigned short __iomem *addr)
return ret;
}
-static inline u16 in_be16(const volatile unsigned short __iomem *addr)
+extern inline u16 in_be16(const volatile unsigned short __iomem *addr)
{
u16 ret;
@@ -202,18 +202,18 @@ static inline u16 in_be16(const volatile unsigned short __iomem *addr)
return ret;
}
-static inline void out_le16(volatile unsigned short __iomem *addr, u16 val)
+extern inline void out_le16(volatile unsigned short __iomem *addr, u16 val)
{
__asm__ __volatile__("sync; sthbrx %1,0,%2" : "=m" (*addr) :
"r" (val), "r" (addr));
}
-static inline void out_be16(volatile unsigned short __iomem *addr, u16 val)
+extern inline void out_be16(volatile unsigned short __iomem *addr, u16 val)
{
__asm__ __volatile__("sync; sth%U0%X0 %1,%0" : "=m" (*addr) : "r" (val));
}
-static inline u32 in_le32(const volatile unsigned __iomem *addr)
+extern inline u32 in_le32(const volatile unsigned __iomem *addr)
{
u32 ret;
@@ -224,7 +224,7 @@ static inline u32 in_le32(const volatile unsigned __iomem *addr)
return ret;
}
-static inline u32 in_be32(const volatile unsigned __iomem *addr)
+extern inline u32 in_be32(const volatile unsigned __iomem *addr)
{
u32 ret;
@@ -234,13 +234,13 @@ static inline u32 in_be32(const volatile unsigned __iomem *addr)
return ret;
}
-static inline void out_le32(volatile unsigned __iomem *addr, u32 val)
+extern inline void out_le32(volatile unsigned __iomem *addr, u32 val)
{
__asm__ __volatile__("sync; stwbrx %1,0,%2" : "=m" (*addr) :
"r" (val), "r" (addr));
}
-static inline void out_be32(volatile unsigned __iomem *addr, u32 val)
+extern inline void out_be32(volatile unsigned __iomem *addr, u32 val)
{
__asm__ __volatile__("sync; stw%U0%X0 %1,%0" : "=m" (*addr) : "r" (val));
}
diff --git a/arch/powerpc/include/asm/mmu.h b/arch/powerpc/include/asm/mmu.h
index 209103e..2e0e292 100644
--- a/arch/powerpc/include/asm/mmu.h
+++ b/arch/powerpc/include/asm/mmu.h
@@ -475,6 +475,10 @@ extern void print_bats(void);
#define BOOKE_PAGESZ_256GB 14
#define BOOKE_PAGESZ_1TB 15
+#define TLBIVAX_ALL 4
+#define TLBIVAX_TLB0 0
+#define TLBIVAX_TLB1 8
+
#ifdef CONFIG_E500
#ifndef __ASSEMBLY__
extern void set_tlb(u8 tlb, u32 epn, u64 rpn,
diff --git a/arch/powerpc/include/asm/mp.h b/arch/powerpc/include/asm/mp.h
index 3ffa30b..fe490ba 100644
--- a/arch/powerpc/include/asm/mp.h
+++ b/arch/powerpc/include/asm/mp.h
@@ -28,4 +28,10 @@ void cpu_mp_lmb_reserve(struct lmb *lmb);
u32 determine_mp_bootpg(void);
int is_core_disabled(int nr);
+#ifdef CONFIG_E6500
+#define thread_to_core(x) (x >> 1)
+#else
+#define thread_to_core(x) (x)
+#endif
+
#endif
diff --git a/arch/powerpc/include/asm/processor.h b/arch/powerpc/include/asm/processor.h
index dc009d6..36695e2 100644
--- a/arch/powerpc/include/asm/processor.h
+++ b/arch/powerpc/include/asm/processor.h
@@ -486,11 +486,13 @@
#define SPRN_L2CFG0 0x207 /* L2 Cache Configuration Register 0 */
#define SPRN_L1CSR0 0x3f2 /* L1 Data Cache Control and Status Register 0 */
#define L1CSR0_CPE 0x00010000 /* Data Cache Parity Enable */
+#define L1CSR0_CUL 0x00000400 /* (D-)Cache Unable to Lock */
#define L1CSR0_DCLFR 0x00000100 /* D-Cache Lock Flash Reset */
#define L1CSR0_DCFI 0x00000002 /* Data Cache Flash Invalidate */
#define L1CSR0_DCE 0x00000001 /* Data Cache Enable */
#define SPRN_L1CSR1 0x3f3 /* L1 Instruction Cache Control and Status Register 1 */
#define L1CSR1_CPE 0x00010000 /* Instruction Cache Parity Enable */
+#define L1CSR1_ICUL 0x00000400 /* I-Cache Unable to Lock */
#define L1CSR1_ICLFR 0x00000100 /* I-Cache Lock Flash Reset */
#define L1CSR1_ICFI 0x00000002 /* Instruction Cache Flash Invalidate */
#define L1CSR1_ICE 0x00000001 /* Instruction Cache Enable */
@@ -513,6 +515,7 @@
#define SPRN_TLB0CFG 0x2B0 /* TLB 0 Config Register */
#define SPRN_TLB1CFG 0x2B1 /* TLB 1 Config Register */
+#define TLBnCFG_NENTRY_MASK 0x00000fff
#define SPRN_TLB0PS 0x158 /* TLB 0 Page Size Register */
#define SPRN_TLB1PS 0x159 /* TLB 1 Page Size Register */
#define SPRN_MMUCSR0 0x3f4 /* MMU control and status register 0 */
@@ -948,6 +951,7 @@
#define PVR_VER_E500_V2 0x8021
#define PVR_VER_E500MC 0x8023
#define PVR_VER_E5500 0x8024
+#define PVR_VER_E6500 0x8040
#define PVR_86xx 0x80040000
@@ -1075,8 +1079,6 @@
#define SVR_P1012 0x80E501
#define SVR_P1013 0x80E700
#define SVR_P1014 0x80F101
-#define SVR_P1015 0x80E502
-#define SVR_P1016 0x80E503
#define SVR_P1017 0x80F700
#define SVR_P1020 0x80E400
#define SVR_P1021 0x80E401
@@ -1089,7 +1091,6 @@
#define SVR_P2040 0x821000
#define SVR_P2041 0x821001
#define SVR_P3041 0x821103
-#define SVR_P3060 0x820002
#define SVR_P4040 0x820100
#define SVR_P4080 0x820000
#define SVR_P5010 0x822100
@@ -1158,6 +1159,7 @@ struct cpu_type {
};
struct cpu_type *identify_cpu(u32 ver);
+int fixup_cpu(void);
#if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx)
#define CPU_TYPE_ENTRY(n, v, nc) \