diff options
| author | York Sun <york.sun@nxp.com> | 2016-12-28 08:43:29 -0800 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2017-01-04 19:40:14 -0500 |
| commit | 53c953841bbb2c094144bff00b41501b635f3153 (patch) | |
| tree | cae389f36eef00eaead2dc64b53b870f38cd1f30 /arch/powerpc/include | |
| parent | 26e79b6547352235fe1bdcda668fe197a8ffdb92 (diff) | |
| download | u-boot-imx-53c953841bbb2c094144bff00b41501b635f3153.zip u-boot-imx-53c953841bbb2c094144bff00b41501b635f3153.tar.gz u-boot-imx-53c953841bbb2c094144bff00b41501b635f3153.tar.bz2 | |
powerpc: mpc85xx: Move CONFIG_SYS_PPC_E500_DEBUG_TLB to Kconfig
Use Kconfig SYS_PPC_E500_DEBUG_TLB and clean up existing macros.
Signed-off-by: York Sun <york.sun@nxp.com>
[trini: Migrate 8572]
Signed-off-by: Tom Rini <trini@konsulko.com>
Diffstat (limited to 'arch/powerpc/include')
| -rw-r--r-- | arch/powerpc/include/asm/config_mpc85xx.h | 14 |
1 files changed, 0 insertions, 14 deletions
diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index 5761218..cbaba36 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -25,7 +25,6 @@ #define CONFIG_SYS_FSL_SEC_MON_BE #if defined(CONFIG_ARCH_MPC8536) -#define CONFIG_SYS_PPC_E500_DEBUG_TLB 1 #define CONFIG_SYS_FSL_SEC_COMPAT 2 #define CONFIG_SYS_FSL_ERRATUM_A004508 #define CONFIG_SYS_FSL_ERRATUM_A005125 @@ -39,13 +38,11 @@ #elif defined(CONFIG_ARCH_MPC8544) #define CONFIG_SYS_FSL_DDRC_GEN2 -#define CONFIG_SYS_PPC_E500_DEBUG_TLB 0 #define CONFIG_SYS_FSL_SEC_COMPAT 2 #define CONFIG_SYS_FSL_ERRATUM_A005125 #elif defined(CONFIG_ARCH_MPC8548) #define CONFIG_SYS_FSL_DDRC_GEN2 -#define CONFIG_SYS_PPC_E500_DEBUG_TLB 0 #define CONFIG_SYS_FSL_SEC_COMPAT 2 #define CONFIG_SYS_FSL_ERRATUM_NMG_DDR120 #define CONFIG_SYS_FSL_ERRATUM_NMG_LBC103 @@ -92,7 +89,6 @@ #define CONFIG_SYS_FSL_ERRATUM_A005125 #elif defined(CONFIG_ARCH_MPC8572) -#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 #define CONFIG_SYS_FSL_SEC_COMPAT 2 #define CONFIG_SYS_FSL_ERRATUM_DDR_115 #define CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134 @@ -101,7 +97,6 @@ #elif defined(CONFIG_ARCH_P1010) #define CONFIG_FSL_SDHC_V2_3 -#define CONFIG_SYS_PPC_E500_DEBUG_TLB 3 #define CONFIG_TSECV2 #define CONFIG_SYS_FSL_SEC_COMPAT 4 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 @@ -126,7 +121,6 @@ /* P1011 is single core version of P1020 */ #elif defined(CONFIG_ARCH_P1011) -#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 #define CONFIG_TSECV2 #define CONFIG_FSL_PCIE_DISABLE_ASPM #define CONFIG_SYS_FSL_SEC_COMPAT 2 @@ -137,7 +131,6 @@ #define CONFIG_SYS_FSL_ERRATUM_A005125 #elif defined(CONFIG_ARCH_P1020) -#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 #define CONFIG_TSECV2 #define CONFIG_FSL_PCIE_DISABLE_ASPM #define CONFIG_SYS_FSL_SEC_COMPAT 2 @@ -150,7 +143,6 @@ #endif #elif defined(CONFIG_ARCH_P1021) -#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 #define CONFIG_TSECV2 #define CONFIG_FSL_PCIE_DISABLE_ASPM #define CONFIG_SYS_FSL_SEC_COMPAT 2 @@ -164,7 +156,6 @@ #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 #elif defined(CONFIG_ARCH_P1022) -#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 #define CONFIG_TSECV2 #define CONFIG_SYS_FSL_SEC_COMPAT 2 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 @@ -192,7 +183,6 @@ /* P1024 is lower end variant of P1020 */ #elif defined(CONFIG_ARCH_P1024) -#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 #define CONFIG_TSECV2 #define CONFIG_FSL_PCIE_DISABLE_ASPM #define CONFIG_SYS_FSL_SEC_COMPAT 2 @@ -205,7 +195,6 @@ /* P1025 is lower end variant of P1021 */ #elif defined(CONFIG_ARCH_P1025) #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 -#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 #define CONFIG_TSECV2 #define CONFIG_FSL_PCIE_DISABLE_ASPM #define CONFIG_SYS_FSL_SEC_COMPAT 2 @@ -218,7 +207,6 @@ #define CONFIG_SYS_FSL_ERRATUM_A005125 #elif defined(CONFIG_ARCH_P2020) -#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 #define CONFIG_SYS_FSL_SEC_COMPAT 2 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 #define CONFIG_SYS_FSL_ERRATUM_ESDHC_A001 @@ -433,7 +421,6 @@ #define CONFIG_ESDHC_HC_BLK_ADDR #elif defined(CONFIG_ARCH_BSC9132) -#define CONFIG_SYS_PPC_E500_DEBUG_TLB 3 #define CONFIG_FSL_SDHC_V2_3 #define CONFIG_TSECV2 #define CONFIG_SYS_FSL_SEC_COMPAT 4 @@ -721,7 +708,6 @@ defined(CONFIG_PPC_T1014) || defined(CONFIG_PPC_T1013) #elif defined(CONFIG_ARCH_C29X) #define CONFIG_FSL_SDHC_V2_3 -#define CONFIG_SYS_PPC_E500_DEBUG_TLB 3 #define CONFIG_TSECV2_1 #define CONFIG_SYS_FSL_SEC_COMPAT 6 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 |