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| author | Scott Wood <scottwood@freescale.com> | 2013-05-15 17:50:13 -0500 |
|---|---|---|
| committer | Andy Fleming <afleming@freescale.com> | 2013-06-20 17:08:49 -0500 |
| commit | 8212519254bc3ea94d959f56f10061849aa07b26 (patch) | |
| tree | 9e9215a35509b017d7927f7ca213fa47dcc1a423 /arch/powerpc/include/asm | |
| parent | 362ee04b797d02117e48312010974d69c325be60 (diff) | |
| download | u-boot-imx-8212519254bc3ea94d959f56f10061849aa07b26.zip u-boot-imx-8212519254bc3ea94d959f56f10061849aa07b26.tar.gz u-boot-imx-8212519254bc3ea94d959f56f10061849aa07b26.tar.bz2 | |
powerpc/mpc85xx: work around erratum A-006593
Erratum A-006593 is "Atomic store may report failure but still allow
the store data to be visible".
The workaround is: "Set CoreNet Platform Cache register CPCHDBCR0 bit
21 to 1'b1. This may have a small impact on synthetic write bandwidth
benchmarks but should have a negligible impact on real code."
Signed-off-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Diffstat (limited to 'arch/powerpc/include/asm')
| -rw-r--r-- | arch/powerpc/include/asm/config_mpc85xx.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index 6b1d3c4..1d46b14 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -555,6 +555,7 @@ #define CONFIG_SYS_FSL_ERRATUM_A004468 #define CONFIG_SYS_FSL_ERRATUM_A_004934 #define CONFIG_SYS_FSL_ERRATUM_A005871 +#define CONFIG_SYS_FSL_ERRATUM_A006593 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 #define CONFIG_SYS_FSL_PCI_VER_3_X @@ -576,6 +577,7 @@ #define CONFIG_SYS_FSL_USB1_PHY_ENABLE #define CONFIG_SYS_FSL_ERRATUM_A_004934 #define CONFIG_SYS_FSL_ERRATUM_A005871 +#define CONFIG_SYS_FSL_ERRATUM_A006593 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 #ifdef CONFIG_PPC_B4860 |