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| author | Stefan Roese <sr@denx.de> | 2010-07-21 11:08:27 +0200 |
|---|---|---|
| committer | Stefan Roese <sr@denx.de> | 2010-07-23 09:54:28 +0200 |
| commit | b995d7cb2c1e47305cd7feb2513ed37d30f8edd3 (patch) | |
| tree | 67ece77e91c2b489ccbdd53000a7a4d33176e623 /arch/powerpc/cpu | |
| parent | 897d6abc50e95fb57fa6952c27deae5776ba08cc (diff) | |
| download | u-boot-imx-b995d7cb2c1e47305cd7feb2513ed37d30f8edd3.zip u-boot-imx-b995d7cb2c1e47305cd7feb2513ed37d30f8edd3.tar.gz u-boot-imx-b995d7cb2c1e47305cd7feb2513ed37d30f8edd3.tar.bz2 | |
ppc4xx: DDR/ECC: Use correct macros to clear error status
Use the correct macro instead of the hardcoded 0x4c to clear the ECC
status in the 440/460 DDR(2) error status register after ECC
initialization.
Also the non-440 parts (405EX(r) right now) and the IBM DDR PPC variants
(440GX) use a different registers to clear this error status. Use the
correct ones.
Signed-off-by: Stefan Roese <sr@denx.de>
Diffstat (limited to 'arch/powerpc/cpu')
| -rw-r--r-- | arch/powerpc/cpu/ppc4xx/ecc.c | 21 |
1 files changed, 20 insertions, 1 deletions
diff --git a/arch/powerpc/cpu/ppc4xx/ecc.c b/arch/powerpc/cpu/ppc4xx/ecc.c index f105605..49f28d9 100644 --- a/arch/powerpc/cpu/ppc4xx/ecc.c +++ b/arch/powerpc/cpu/ppc4xx/ecc.c @@ -130,7 +130,26 @@ static void program_ecc_addr(unsigned long start_address, /* clear ECC error repoting registers */ mtsdram(SDRAM_ECCES, 0xffffffff); - mtdcr(0x4c, 0xffffffff); +#if defined(CONFIG_SDRAM_PPC4xx_IBM_DDR) + /* + * IBM DDR(1) core (440GX): + * Clear Mx bits in SDRAM0_BESR0/1 + */ + mtsdram(SDRAM0_BESR0, 0xffffffff); + mtsdram(SDRAM0_BESR1, 0xffffffff); +#elif defined(CONFIG_440) + /* + * 440/460 DDR2 core: + * Clear EMID (Error PLB Master ID) in MQ0_ESL + */ + mtdcr(SDRAM_ERRSTATLL, 0xfff00000); +#else + /* + * 405EX(r) DDR2 core: + * Clear M0ID (Error PLB Master ID) in SDRAM_BESR + */ + mtsdram(SDRAM_BESR, 0xf0000000); +#endif mtsdram(SDRAM_MCOPT1, (mcopt1 & ~SDRAM_MCOPT1_MCHK_MASK) | SDRAM_MCOPT1_MCHK_CHK_REP); |