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authorKumar Gala <galak@kernel.crashing.org>2011-10-31 22:13:26 -0500
committerKumar Gala <galak@kernel.crashing.org>2011-11-08 08:36:51 -0600
commit50cf3d17ce021fc6156d41abfbaa5490e8238c3b (patch)
tree4e2968325c89314978c6fbae214465a76c803b72 /arch/powerpc/cpu
parenta311db6941791617cb4b6bc3c67b47a8b1132e95 (diff)
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powerpc/85xx: Add support for Book-E MMU Arch v2.0
A few of the config registers changed definition between MMU v1.0 and MMUv2.0. The new e6500 core from Freescale implements v2.0 of the architecture. Specifically, how we determine the size of TLB entries we support in the variable size (or TLBCAM/TLB1) array is specified in a new register (TLBnPS - TLB n Page size) instead of via TLBnCFG. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'arch/powerpc/cpu')
-rw-r--r--arch/powerpc/cpu/mpc85xx/tlb.c12
1 files changed, 8 insertions, 4 deletions
diff --git a/arch/powerpc/cpu/mpc85xx/tlb.c b/arch/powerpc/cpu/mpc85xx/tlb.c
index 01a3561..80ad04a 100644
--- a/arch/powerpc/cpu/mpc85xx/tlb.c
+++ b/arch/powerpc/cpu/mpc85xx/tlb.c
@@ -252,16 +252,20 @@ setup_ddr_tlbs_phys(phys_addr_t p_addr, unsigned int memsize_in_meg)
unsigned int tlb_size;
unsigned int wimge = 0;
unsigned int ram_tlb_address = (unsigned int)CONFIG_SYS_DDR_SDRAM_BASE;
- unsigned int max_cam = (mfspr(SPRN_TLB1CFG) >> 16) & 0xf;
+ unsigned int max_cam;
u64 size, memsize = (u64)memsize_in_meg << 20;
#ifdef CONFIG_SYS_PPC_DDR_WIMGE
wimge = CONFIG_SYS_PPC_DDR_WIMGE;
#endif
size = min(memsize, CONFIG_MAX_MEM_MAPPED);
-
- /* Convert (4^max) kB to (2^max) bytes */
- max_cam = max_cam * 2 + 10;
+ if ((mfspr(SPRN_MMUCFG) & MMUCFG_MAVN) == MMUCFG_MAVN_V1) {
+ /* Convert (4^max) kB to (2^max) bytes */
+ max_cam = ((mfspr(SPRN_TLB1CFG) >> 16) & 0xf) * 2 + 10;
+ } else {
+ /* Convert (2^max) kB to (2^max) bytes */
+ max_cam = __ilog2(mfspr(SPRN_TLB1PS)) + 10;
+ }
for (i = 0; size && i < 8; i++) {
int ram_tlb_index = find_free_tlbcam();